riscv/rocket-chip
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replace verilog clock divider with one written in Chisel

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This commit is contained in:
Howard Mao
2016-09-21 20:17:32 -07:00
parent cbd702e48e
commit cd96a66ba6
5 changed files with 43 additions and 39 deletions
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vsim/Makefrag
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@ -9,7 +9,6 @@ bb_vsrcs = $(base_dir)/vsrc/DebugTransportModuleJtag.v \
$(base_dir)/vsrc/AsyncMailbox.v \
$(base_dir)/vsrc/AsyncResetReg.v \
$(base_dir)/vsrc/AsyncSetReg.v \
$(base_dir)/vsrc/ClockDivider.v \
sim_vsrcs = \