From cc7783404df6dd87b7eaef3aa93b2b80906e8a13 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 12 Sep 2013 16:09:53 -0700 Subject: [PATCH] Add memory command M_XA_XOR --- uncore/src/main/scala/consts.scala | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/uncore/src/main/scala/consts.scala b/uncore/src/main/scala/consts.scala index 15bfee4d..3a1a8482 100644 --- a/uncore/src/main/scala/consts.scala +++ b/uncore/src/main/scala/consts.scala @@ -21,13 +21,14 @@ trait MemoryOpConstants { val M_XWR = Bits("b00001"); // int store val M_PFR = Bits("b00010"); // prefetch with intent to read val M_PFW = Bits("b00011"); // prefetch with intent to write + val M_XA_SWAP = Bits("b00100"); val M_FENCE = Bits("b00101"); // memory fence val M_XLR = Bits("b00110"); val M_XSC = Bits("b00111"); val M_XA_ADD = Bits("b01000"); - val M_XA_SWAP = Bits("b01001"); - val M_XA_AND = Bits("b01010"); - val M_XA_OR = Bits("b01011"); + val M_XA_XOR = Bits("b01001"); + val M_XA_OR = Bits("b01010"); + val M_XA_AND = Bits("b01011"); val M_XA_MIN = Bits("b01100"); val M_XA_MAX = Bits("b01101"); val M_XA_MINU = Bits("b01110"); @@ -35,7 +36,7 @@ trait MemoryOpConstants { val M_INV = Bits("b10000"); // write back and invalidate line val M_CLN = Bits("b10001"); // write back line - def isAMO(cmd: Bits) = cmd(3) + def isAMO(cmd: Bits) = cmd(3) || cmd === M_XA_SWAP def isPrefetch(cmd: Bits) = cmd === M_PFR || cmd === M_PFW def isRead(cmd: Bits) = cmd === M_XRD || cmd === M_XLR || isAMO(cmd) def isWrite(cmd: Bits) = cmd === M_XWR || cmd === M_XSC || isAMO(cmd)