riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Respect ISA requirements on interrupt priority order

Browse Source 
a62e76cb16
This commit is contained in:
Andrew Waterman 2017-08-17 21:27:08 -07:00
parent e945f6e265
commit cbe7c51b50
1 changed files with 9 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
src/main/scala/rocket/CSR.scala
View File

@ -756,12 +756,15 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
} }
} }
def chooseInterrupt(masks: Seq[UInt]) = { def chooseInterrupt(masks: Seq[UInt]): (Bool, UInt) = {
// we can't simply choose the highest-numbered interrupt, because timer val nonstandard = supported_interrupts.getWidth-1 to 12 by -1
// interrupts are in the wrong place in mip. // MEI, MSI, MTI, SEI, SSI, STI, UEI, USI, UTI
val timerMask = UInt(0xF0, xLen) val standard = Seq(11, 3, 7, 9, 1, 5, 8, 0, 4)
val masked = masks.map(m => Cat(m.padTo(xLen) & ~timerMask, m.padTo(xLen) & timerMask)) val priority = nonstandard ++ standard
(masks.map(_.orR).reduce(_||_), Log2(masked.asUInt)(log2Ceil(xLen)-1, 0)) val paddedMasks = masks.reverse.map(_.padTo(xLen))
val any = paddedMasks.flatMap(m => priority.map(i => m(i))).reduce(_||_)
val which = PriorityMux(paddedMasks.flatMap(m => priority.map(i => (m(i), i.U))))
(any, which)
} }
def readModifyWriteCSR(cmd: UInt, rdata: UInt, wdata: UInt) = def readModifyWriteCSR(cmd: UInt, rdata: UInt, wdata: UInt) =