riscv/rocket-chip
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make sure junctions and uncore unittests both run

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This commit is contained in:
Howard Mao 2016-09-21 18:45:12 -07:00
parent 9acb352cf6
commit cbd702e48e
1 changed files with 5 additions and 16 deletions
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21
src/main/scala/unittest/Configs.scala
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@ -9,8 +9,10 @@ import cde.{Parameters, Config, CDEMatchError}
import coreplex._
import rocketchip._
class WithJunctionsUnitTests extends Config(
class WithUnitTests extends Config(
(pname, site, here) => pname match {
case uncore.tilelink.TLId => "L1toL2"
case NCoreplexExtClients => 0
case RegressionTestNames => LinkedHashSet("rv64ui-p-simple")
case UnitTests => (p: Parameters) => {
TestGeneration.addSuite(DefaultTestSuites.groundtest64("p")) // TODO why
@ -18,20 +20,7 @@ class WithJunctionsUnitTests extends Config(
Seq(
Module(new junctions.MultiWidthFifoTest),
Module(new junctions.NastiMemoryDemuxTest()(p)),
Module(new junctions.HastiTest()(p)))
}
case _ => throw new CDEMatchError
})
class WithUncoreUnitTests extends Config(
(pname, site, here) => pname match {
case NCoreplexExtClients => 0
case uncore.tilelink.TLId => "L1toL2"
case RegressionTestNames => LinkedHashSet("rv64ui-p-simple")
case UnitTests => (p: Parameters) => {
TestGeneration.addSuite(DefaultTestSuites.groundtest64("p")) // TODO why
TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
Seq(
Module(new junctions.HastiTest()(p)),
Module(new uncore.devices.ROMSlaveTest()(p)),
Module(new uncore.devices.TileLinkRAMTest()(p)),
Module(new uncore.tilelink2.TLFuzzRAMTest))
@ -39,4 +28,4 @@ class WithUncoreUnitTests extends Config(
case _ => throw new CDEMatchError
})
class UnitTestConfig extends Config(new WithUncoreUnitTests ++ new WithJunctionsUnitTests ++ new BaseConfig)
class UnitTestConfig extends Config(new WithUnitTests ++ new BaseConfig)