riscv/rocket-chip
1
0 Fork 0
Code Releases Activity

debug: remove old Verilog DebugTransportModuleJtag file as it has been replaced by Chisel version

Browse Source
This commit is contained in:
Megan Wachs committed 2017-03-27 21:24:44 -07:00
1 parent bb64c92906
commit cbc8d2400a
2 files changed
+1 -338
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

vsim/Makefrag
+1 -1
View File
@@ -4,7 +4,7 @@
# Verilog sources
bb_vsrcs = $(base_dir)/vsrc/DebugTransportModuleJtag.v \
bb_vsrcs = \
$(base_dir)/vsrc/jtag_vpi.v \
$(base_dir)/vsrc/ClockDivider2.v \
$(base_dir)/vsrc/AsyncResetReg.v \