riscv/rocket-chip
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Use Mem instead of Vec[Reg]

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This commit is contained in:
Andrew Waterman
2014-05-18 19:25:43 -07:00
parent e91e12ed88
commit cbb37ccc3e
2 changed files with 36 additions and 39 deletions
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2
rocket/src/main/scala/tlb.scala
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@ -97,7 +97,7 @@ class TLB(entries: Int)(implicit conf: AddressSpaceConfiguration) extends Module
val r_refill_waddr = Reg(UInt())
val tag_cam = Module(new RocketCAM(entries, conf.asidBits+conf.vpnBits))
val tag_ram = Vec.fill(entries){Reg(io.ptw.resp.bits.ppn.clone)}
val tag_ram = Mem(io.ptw.resp.bits.ppn.clone, entries)
val lookup_tag = Cat(io.req.bits.asid, io.req.bits.vpn).toUInt
tag_cam.io.clear := io.ptw.invalidate