riscv/rocket-chip
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provide store data with cache response

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This commit is contained in:
Andrew Waterman 2012-11-16 21:15:13 -08:00
parent 9e010beffe
commit cb8ac73045
1 changed files with 2 additions and 0 deletions
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rocket/src/main/scala/nbdcache.scala
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@ -666,6 +666,7 @@ class HellaCacheResp(implicit conf: DCacheConfig) extends Bundle {
val data = Bits(width = conf.databits) val data = Bits(width = conf.databits)
val data_subword = Bits(width = conf.databits) val data_subword = Bits(width = conf.databits)
val tag = Bits(width = conf.reqtagbits) val tag = Bits(width = conf.reqtagbits)
val store_data = Bits(width = conf.databits)
override def clone = new HellaCacheResp().asInstanceOf[this.type] override def clone = new HellaCacheResp().asInstanceOf[this.type]
} }
@ -930,6 +931,7 @@ class HellaCache(implicit conf: DCacheConfig) extends Component {
io.cpu.resp.bits.typ := s2_req.typ io.cpu.resp.bits.typ := s2_req.typ
io.cpu.resp.bits.data := loadgen.word io.cpu.resp.bits.data := loadgen.word
io.cpu.resp.bits.data_subword := loadgen.byte io.cpu.resp.bits.data_subword := loadgen.byte
io.cpu.resp.bits.store_data := s2_req.data
val xact_init_arb = (new Arbiter(2)) { new TransactionInit } val xact_init_arb = (new Arbiter(2)) { new TransactionInit }
xact_init_arb.io.in(0) <> wb.io.mem_req xact_init_arb.io.in(0) <> wb.io.mem_req