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fix trace generator addresses

This commit is contained in:
Howard Mao 2016-07-28 17:56:14 -07:00
parent 8a7fc75b53
commit cb86aaa46b
2 changed files with 6 additions and 6 deletions

View File

@ -56,7 +56,7 @@ import cde.{Parameters, Field}
// (This is a way to generate a wider range of addresses without having
// to repeatedly recompile with a different address bag.)
case object AddressBag extends Field[List[Int]]
case object AddressBag extends Field[List[BigInt]]
trait HasTraceGenParams {
implicit val p: Parameters
@ -480,7 +480,7 @@ class TraceGenerator(id: Int)
// Wire up interface to memory
io.mem.req.valid := reqValid
io.mem.req.bits.addr := reqAddr + UInt(baseAddr)
io.mem.req.bits.addr := reqAddr
io.mem.req.bits.data := reqData
io.mem.req.bits.typ := MT_D
io.mem.req.bits.cmd := reqCmd

View File

@ -196,17 +196,17 @@ class WithTraceGen extends Config(
val nSets = 32 // L2 NSets
val nWays = 1
val blockOffset = site(CacheBlockOffsetBits)
List.tabulate(2 * nWays) { i =>
val baseAddr = site(GlobalAddrMap)("mem").start
List.tabulate(4 * nWays) { i =>
Seq.tabulate(2) { j => (i * nSets + j * 8) << blockOffset }
}.flatten
}.flatten.map(addr => baseAddr + BigInt(addr))
}
case UseAtomics => true
case _ => throw new CDEMatchError
},
knobValues = {
case "L1D_SETS" => 16
case "L1D_WAYS" => 1
case "L2_CAPACITY_IN_KB" => 32 * 64 / 1024
case "L2_WAYS" => 1
})
class GroundTestConfig extends Config(new WithGroundTest ++ new BaseConfig)