fix trace generator addresses
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8a7fc75b53
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@ -56,7 +56,7 @@ import cde.{Parameters, Field}
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// (This is a way to generate a wider range of addresses without having
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// to repeatedly recompile with a different address bag.)
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case object AddressBag extends Field[List[Int]]
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case object AddressBag extends Field[List[BigInt]]
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trait HasTraceGenParams {
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implicit val p: Parameters
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@ -480,7 +480,7 @@ class TraceGenerator(id: Int)
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// Wire up interface to memory
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io.mem.req.valid := reqValid
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io.mem.req.bits.addr := reqAddr + UInt(baseAddr)
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io.mem.req.bits.addr := reqAddr
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io.mem.req.bits.data := reqData
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io.mem.req.bits.typ := MT_D
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io.mem.req.bits.cmd := reqCmd
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@ -196,17 +196,17 @@ class WithTraceGen extends Config(
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val nSets = 32 // L2 NSets
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val nWays = 1
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val blockOffset = site(CacheBlockOffsetBits)
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List.tabulate(2 * nWays) { i =>
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val baseAddr = site(GlobalAddrMap)("mem").start
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List.tabulate(4 * nWays) { i =>
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Seq.tabulate(2) { j => (i * nSets + j * 8) << blockOffset }
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}.flatten
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}.flatten.map(addr => baseAddr + BigInt(addr))
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}
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case UseAtomics => true
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case _ => throw new CDEMatchError
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},
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knobValues = {
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case "L1D_SETS" => 16
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case "L1D_WAYS" => 1
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case "L2_CAPACITY_IN_KB" => 32 * 64 / 1024
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case "L2_WAYS" => 1
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})
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class GroundTestConfig extends Config(new WithGroundTest ++ new BaseConfig)
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