More broadcast hub bugfixes
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		@@ -276,17 +276,17 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
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    when(req_data.ready && req_data.valid) {
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					    when(req_data.ready && req_data.valid) {
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      pop_data := UFix(1) << tile_id 
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					      pop_data := UFix(1) << tile_id 
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      mem_cnt  := mem_cnt_next
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					      mem_cnt  := mem_cnt_next
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    }
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      when(mem_cnt_next === UFix(0)) {
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					      when(mem_cnt_next === UFix(0)) {
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        pop_dep := UFix(1) << tile_id
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					        pop_dep := UFix(1) << tile_id
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        trigger := Bool(false)
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					        trigger := Bool(false)
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      }
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					      }
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    }
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					    }
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					  }
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  def doMemReqRead(req_cmd: ioDecoupled[MemReqCmd], trigger: Bool) {
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					  def doMemReqRead(req_cmd: ioDecoupled[MemReqCmd], trigger: Bool) {
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    req_cmd.valid := Bool(true)
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					    req_cmd.valid := Bool(true)
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    req_cmd.bits.rw := Bool(false)
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					    req_cmd.bits.rw := Bool(false)
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    when(req_cmd.ready ) {
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					    when(req_cmd.ready) {
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      trigger := Bool(false)
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					      trigger := Bool(false)
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    }
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					    }
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  }
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					  }
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@@ -535,10 +535,11 @@ class CoherenceHubBroadcast extends CoherenceHub  with FourStateCoherence{
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      rep.bits.t_type := getTransactionReplyType(t_type_arr(ack_idx), sh_count_arr(ack_idx))
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					      rep.bits.t_type := getTransactionReplyType(t_type_arr(ack_idx), sh_count_arr(ack_idx))
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      rep.bits.tile_xact_id := tile_xact_id_arr(ack_idx)
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					      rep.bits.tile_xact_id := tile_xact_id_arr(ack_idx)
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      rep.bits.global_xact_id := ack_idx
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					      rep.bits.global_xact_id := ack_idx
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      rep.valid := (UFix(j) === init_tile_id_arr(ack_idx)) && send_x_rep_ack_arr.toBits.orR
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					      val do_send_ack = (UFix(j) === init_tile_id_arr(ack_idx)) && send_x_rep_ack_arr.toBits.orR
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					      rep.valid := do_send_ack
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					      sent_x_rep_ack_arr(ack_idx) := do_send_ack
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    }
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					    }
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  }
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					  }
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  sent_x_rep_ack_arr(ack_idx) := !io.mem.resp.valid
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  // If there were a ready signal due to e.g. intervening network use:
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					  // If there were a ready signal due to e.g. intervening network use:
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  //io.mem.resp.ready  := io.tiles(init_tile_id_arr.read(mem_idx)).xact_rep.ready
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					  //io.mem.resp.ready  := io.tiles(init_tile_id_arr.read(mem_idx)).xact_rep.ready
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