allow direct instatiation of arbitrary non-caching groundtests

src/main/scala/DirectGroundTest.scala

@@ -0,0 +1,40 @@
+package rocketchip
+
+import Chisel._
+import cde.{Parameters, Field}
+import groundtest._
+import uncore.tilelink._
+import uncore.agents._
+
+class DirectGroundTestTop(topParams: Parameters) extends Module
+    with HasTopLevelParameters {
+  implicit val p = topParams
+  val io = new TopIO
+
+  // Not using the debug 
+  io.debug.req.ready := Bool(false)
+  io.debug.resp.valid := Bool(false)
+
+  require(io.mmio_axi.isEmpty && io.mmio_ahb.isEmpty && io.mmio_tl.isEmpty)
+  require(io.mem_ahb.isEmpty && io.mem_tl.isEmpty)
+  require(nMemChannels == 1)
+  require(nTiles == 1)
+
+  val test = p(BuildGroundTest)(outermostParams.alterPartial({
+    case GroundTestId => 0
+    case CacheName => "L1D"
+  }))
+  require(test.io.cache.size == 0)
+  require(test.io.mem.size == nBanksPerMemChannel)
+  require(test.io.ptw.size == 0)
+
+  when (test.io.finished) { stop() }
+
+  val mem_ic = Module(new TileLinkMemoryInterconnect(
+    nBanksPerMemChannel, nMemChannels)(outermostParams))
+
+  mem_ic.io.in <> test.io.mem
+  io.mem_axi.zip(mem_ic.io.out).foreach { case (nasti, tl) =>
+    TopUtils.connectTilelinkNasti(nasti, tl)(outermostParams)
+  }
+}

src/main/scala/DirectMemtest.scala

@@ -1,52 +0,0 @@
-package rocketchip
-
-import Chisel._
-import cde.{Parameters, Field}
-import groundtest._
-import uncore.tilelink._
-
-trait HasDirectMemtestParameters {
-  implicit val p: Parameters
-  lazy val tileSettings = p(GroundTestKey)(0)
-  lazy val nGens = tileSettings.uncached
-}
-
-class MemtestGenerators(implicit val p: Parameters) extends Module
-    with HasDirectMemtestParameters {
-  val io = new Bundle {
-    val mem = Vec(nGens, new ClientUncachedTileLinkIO)
-    val finished = Bool(OUTPUT)
-  }
-
-  val generators =
-    (0 until nGens).map(id => Module(new UncachedTileLinkGenerator(id)))
-
-  io.mem <> generators.map(_.io.mem)
-  io.finished := generators.map(_.io.finished).reduce(_ && _)
-}
-
-class DirectMemtestTop(topParams: Parameters) extends Module
-    with HasTopLevelParameters
-    with HasDirectMemtestParameters {
-  implicit val p = topParams
-  val io = new TopIO
-
-  // Not using the debug 
-  io.debug.req.ready := Bool(false)
-  io.debug.resp.valid := Bool(false)
-
-  require(io.mmio_axi.isEmpty && io.mmio_ahb.isEmpty && io.mmio_tl.isEmpty)
-  require(io.mem_ahb.isEmpty && io.mem_tl.isEmpty)
-  require(nBanksPerMemChannel == nGens)
-  require(nMemChannels == 1)
-  require(nTiles == 1)
-
-  val memtest = Module(new MemtestGenerators()(outermostParams))
-  val mem_ic = Module(new TileLinkMemoryInterconnect(nGens, 1)(outermostParams))
-
-  mem_ic.io.in <> memtest.io.mem
-  io.mem_axi.zip(mem_ic.io.out).foreach { case (nasti, tl) =>
-    TopUtils.connectTilelinkNasti(nasti, tl)(outermostParams)
-  }
-  when (memtest.io.finished) { stop() }
-}

src/main/scala/TestConfigs.scala

@@ -251,6 +251,7 @@ class WithPCIeMockupTest extends Config(
       }
     case _ => throw new CDEMatchError
   })
+
 class PCIeMockupTestConfig extends Config(
   new WithPCIeMockupTest ++ new GroundTestConfig)
 
@@ -258,7 +259,6 @@ class WithDirectMemtest extends Config(
   (pname, site, here) => {
     val nGens = 8
     pname match {
-      case GroundTestId => 0
       case GroundTestKey => Seq(GroundTestTileSettings(uncached = nGens))
       case GeneratorKey => GeneratorParameters(
         maxRequests = 1024,
@@ -267,9 +267,36 @@ class WithDirectMemtest extends Config(
       case NAcquireTransactors => nGens - 2
       case MIFTagBits => Dump("MIF_TAG_BITS", 2)
       case NBanksPerMemoryChannel => nGens
+      case BuildGroundTest =>
+        (p: Parameters) => Module(new GeneratorTest()(p))
       case _ => throw new CDEMatchError
     }
   })
 
+class WithDirectComparator extends Config(
+  (pname, site, here) => pname match {
+    case GroundTestKey => Seq.fill(site(NTiles)) {
+      GroundTestTileSettings(uncached = site(ComparatorKey).targets.size)
+    }
+    case BuildGroundTest =>
+      (p: Parameters) => Module(new ComparatorCore()(p))
+    case ComparatorKey => ComparatorParameters(
+      targets    = Seq(0L, 0x100L),
+      width      = 8,
+      operations = 1000,
+      atomics    = site(UseAtomics),
+      prefetches = site("COMPARATOR_PREFETCHES"))
+    case UseFPU => false
+    case UseAtomics => false
+    case "COMPARATOR_PREFETCHES" => false
+    // Hax Hax Hax
+    case NAcquireTransactors => 0
+    case MIFTagBits => Dump("MIF_TAG_BITS", 2)
+    case NBanksPerMemoryChannel => site(ComparatorKey).targets.size
+    case _ => throw new CDEMatchError
+  })
+
 class DirectMemtestConfig extends Config(
   new WithDirectMemtest ++ new GroundTestConfig)
+class DirectComparatorConfig extends Config(
+  new WithDirectComparator ++ new GroundTestConfig)