riscv/rocket-chip
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Reformatted hammer directory, added parent scripts to repo, as well as README.

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This commit is contained in:
Adam Izraelevitz 2014-02-28 15:57:46 -08:00
parent f14f386b4f
commit cb14baab88
1 changed files with 3 additions and 2 deletions
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src/main/scala/RocketChip.scala
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@ -251,9 +251,10 @@ class Top extends Module {
implicit val l2 = L2CoherenceAgentConfiguration(tl, NL2_REL_XACTS, NL2_ACQ_XACTS) implicit val l2 = L2CoherenceAgentConfiguration(tl, NL2_REL_XACTS, NL2_ACQ_XACTS)
implicit val uc = UncoreConfiguration(l2, tl, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64) implicit val uc = UncoreConfiguration(l2, tl, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64)
val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 38) val isize = RangeParam("i",7,7,9)
val ic = ICacheConfig(math.pow(2, isize.getValue).toInt, 2, ntlb = 8, nbtb = 38)
val dsize = RangeParam("dsize",7,7,9) val dsize = RangeParam("d",7,7,9)
val dc = DCacheConfig(math.pow(2, dsize.getValue).toInt, 4, ntlb = 8, nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates) val dc = DCacheConfig(math.pow(2, dsize.getValue).toInt, 4, ntlb = 8, nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates)
//val dc = DCacheConfig(128, 4, ntlb = 8, nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates) //val dc = DCacheConfig(128, 4, ntlb = 8, nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates)