tilelink2: Hints are not special

Hints have a TransferSize limit just like all other message types.

src/main/scala/uncore/tilelink2/Edges.scala

@@ -378,7 +378,7 @@ class TLEdgeOut(
 
   def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
     require (manager.anySupportHint)
-    val legal = manager.supportsHint(toAddress)
+    val legal = manager.supportsHint(toAddress, lgSize)
     val a = Wire(new TLBundleA(bundle))
     a.opcode  := TLMessages.Hint
     a.param   := param
@@ -571,7 +571,7 @@ class TLEdgeIn(
 
   def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
     require (client.anySupportHint)
-    val legal = client.supportsHint(toSource)
+    val legal = client.supportsHint(toSource, lgSize)
     val b = Wire(new TLBundleB(bundle))
     b.opcode  := TLMessages.Hint
     b.param   := param

src/main/scala/uncore/tilelink2/Fragmenter.scala

@@ -44,7 +44,7 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) exten
     supportsGet        = TransferSizes.none,
     supportsPutFull    = TransferSizes.none,
     supportsPutPartial = TransferSizes.none,
-    supportsHint       = false)
+    supportsHint       = TransferSizes.none)
 
   val node = TLAdapterNode(
     clientFn  = { case Seq(c) => c.copy(clients = c.clients.map(mapClient)) },

src/main/scala/uncore/tilelink2/HintHandler.scala

@@ -9,8 +9,8 @@ import chisel3.internal.sourceinfo.SourceInfo
 class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true) extends LazyModule
 {
   val node = TLAdapterNode(
-    clientFn  = { case Seq(c) => if (supportClients)  c.copy(clients  = c.clients .map(_.copy(supportsHint = true))) else c },
+    clientFn  = { case Seq(c) => if (!supportClients)  c else c.copy(clients  = c.clients .map(_.copy(supportsHint = TransferSizes(1, c.maxTransfer)))) },
-    managerFn = { case Seq(m) => if (supportManagers) m.copy(managers = m.managers.map(_.copy(supportsHint = true))) else m })
+    managerFn = { case Seq(m) => if (!supportManagers) m else m.copy(managers = m.managers.map(_.copy(supportsHint = TransferSizes(1, m.maxTransfer)))) })
 
   lazy val module = new LazyModuleImp(this) {
     val io = new Bundle {
@@ -28,7 +28,7 @@ class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = f
     require (!supportClients || bce)
 
     if (supportManagers) {
-      val handleA = if (passthrough) !edgeOut.manager.supportsHint(edgeIn.address(in.a.bits)) else Bool(true)
+      val handleA = if (passthrough) !edgeOut.manager.supportsHint(edgeIn.address(in.a.bits), edgeIn.size(in.a.bits)) else Bool(true)
       val bypassD = handleA && in.a.bits.opcode === TLMessages.Hint
 
       // Prioritize existing D traffic over HintAck
@@ -50,7 +50,7 @@ class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = f
     }
 
     if (supportClients) {
-      val handleB = if (passthrough) !edgeIn.client.supportsHint(out.b.bits.source) else Bool(true)
+      val handleB = if (passthrough) !edgeIn.client.supportsHint(out.b.bits.source, edgeOut.size(out.b.bits)) else Bool(true)
       val bypassC = handleB && out.b.bits.opcode === TLMessages.Hint
 
       // Prioritize existing C traffic over HintAck

src/main/scala/uncore/tilelink2/Monitor.scala

@@ -72,7 +72,7 @@ object TLMonitor
     }
 
     when (bundle.opcode === TLMessages.Hint) {
-      assert (edge.manager.supportsHint(edge.address(bundle)), "'A' channel carries Hint type unsupported by manager" + extra)
+      assert (edge.manager.supportsHint(edge.address(bundle), bundle.size), "'A' channel carries Hint type unsupported by manager" + extra)
       assert (source_ok, "'A' channel Hint carries invalid source ID" + extra)
       assert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
       assert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
@@ -137,7 +137,7 @@ object TLMonitor
     }
 
     when (bundle.opcode === TLMessages.Hint) {
-      assert (edge.client.supportsHint(bundle.source), "'B' channel carries Hint type unsupported by client" + extra)
+      assert (edge.client.supportsHint(bundle.source, bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
       assert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
       assert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
       assert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)

src/main/scala/uncore/tilelink2/Parameters.scala

@@ -110,7 +110,7 @@ case class TLManagerParameters(
   supportsGet:        TransferSizes = TransferSizes.none,
   supportsPutFull:    TransferSizes = TransferSizes.none,
   supportsPutPartial: TransferSizes = TransferSizes.none,
-  supportsHint:       Boolean       = false,
+  supportsHint:       TransferSizes = TransferSizes.none,
   // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order
   fifoId:             Option[Int]   = None)
 {
@@ -159,7 +159,7 @@ case class TLManagerPortParameters(managers: Seq[TLManagerParameters], beatBytes
   val allSupportGet        = managers.map(_.supportsGet)       .reduce(_ intersect _)
   val allSupportPutFull    = managers.map(_.supportsPutFull)   .reduce(_ intersect _)
   val allSupportPutPartial = managers.map(_.supportsPutPartial).reduce(_ intersect _)
-  val allSupportHint       = managers.map(_.supportsHint)      .reduce(_    &&     _)
+  val allSupportHint       = managers.map(_.supportsHint)      .reduce(_ intersect _)
 
   // Operation supported by at least one outward Managers
   val anySupportAcquire    = managers.map(!_.supportsAcquire.none)   .reduce(_ || _)
@@ -168,7 +168,7 @@ case class TLManagerPortParameters(managers: Seq[TLManagerParameters], beatBytes
   val anySupportGet        = managers.map(!_.supportsGet.none)       .reduce(_ || _)
   val anySupportPutFull    = managers.map(!_.supportsPutFull.none)   .reduce(_ || _)
   val anySupportPutPartial = managers.map(!_.supportsPutPartial.none).reduce(_ || _)
-  val anySupportHint       = managers.map( _.supportsHint)           .reduce(_ || _)
+  val anySupportHint       = managers.map(!_.supportsHint.none)      .reduce(_ || _)
 
   // These return Option[TLManagerParameters] for your convenience
   def find(address: BigInt) = managers.find(_.address.exists(_.contains(address)))
@@ -198,11 +198,7 @@ case class TLManagerPortParameters(managers: Seq[TLManagerParameters], beatBytes
   val supportsGet        = safety_helper(_.supportsGet)        _
   val supportsPutFull    = safety_helper(_.supportsPutFull)    _
   val supportsPutPartial = safety_helper(_.supportsPutPartial) _
-  def supportsHint(address: UInt) = {
+  val supportsHint       = safety_helper(_.supportsHint)       _
-    if (allSupportHint) Bool(true) else {
-      Mux1H(find(address), managers.map(m => Bool(m.supportsHint)))
-    }
-  }
 }
 
 case class TLClientParameters(
@@ -214,7 +210,7 @@ case class TLClientParameters(
   supportsGet:         TransferSizes = TransferSizes.none,
   supportsPutFull:     TransferSizes = TransferSizes.none,
   supportsPutPartial:  TransferSizes = TransferSizes.none,
-  supportsHint:        Boolean       = false)
+  supportsHint:        TransferSizes = TransferSizes.none)
 {
   require (supportsPutFull.contains(supportsPutPartial))
 
@@ -246,7 +242,7 @@ case class TLClientPortParameters(clients: Seq[TLClientParameters]) {
   val allSupportGet        = clients.map(_.supportsGet)       .reduce(_ intersect _)
   val allSupportPutFull    = clients.map(_.supportsPutFull)   .reduce(_ intersect _)
   val allSupportPutPartial = clients.map(_.supportsPutPartial).reduce(_ intersect _)
-  val allSupportHint       = clients.map(_.supportsHint)      .reduce(_    &&     _)
+  val allSupportHint       = clients.map(_.supportsHint)      .reduce(_ intersect _)
 
   // Operation is supported by at least one client
   val anySupportProbe      = clients.map(!_.supportsProbe.none)     .reduce(_ || _)
@@ -255,7 +251,7 @@ case class TLClientPortParameters(clients: Seq[TLClientParameters]) {
   val anySupportGet        = clients.map(!_.supportsGet.none)       .reduce(_ || _)
   val anySupportPutFull    = clients.map(!_.supportsPutFull.none)   .reduce(_ || _)
   val anySupportPutPartial = clients.map(!_.supportsPutPartial.none).reduce(_ || _)
-  val anySupportHint       = clients.map( _.supportsHint)           .reduce(_ || _)
+  val anySupportHint       = clients.map(!_.supportsHint.none)      .reduce(_ || _)
 
   // These return Option[TLClientParameters] for your convenience
   def find(id: Int) = clients.find(_.sourceId.contains(id))
@@ -278,11 +274,7 @@ case class TLClientPortParameters(clients: Seq[TLClientParameters]) {
   val supportsGet        = safety_helper(_.supportsGet)        _
   val supportsPutFull    = safety_helper(_.supportsPutFull)    _
   val supportsPutPartial = safety_helper(_.supportsPutPartial) _
-  def supportsHint(id: UInt) = {
+  val supportsHint       = safety_helper(_.supportsHint)       _
-    if (allSupportHint) Bool(true) else {
-      Mux1H(find(id), clients.map(c => Bool(c.supportsHint)))
-    }
-  }
 }
 
 case class TLBundleParameters(