uncore: more verbose requires
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f3ab23d068
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@ -18,15 +18,16 @@ case class AXI4SlaveParameters(
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interleavedId: Option[Int] = None) // The device will not interleave read responses
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interleavedId: Option[Int] = None) // The device will not interleave read responses
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{
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{
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address.foreach { a => require (a.finite) }
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address.foreach { a => require (a.finite) }
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address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y)) }
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address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap") }
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val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
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val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
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val maxTransfer = max(supportsWrite.max, supportsRead.max)
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val maxTransfer = max(supportsWrite.max, supportsRead.max)
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val maxAddress = address.map(_.max).max
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val maxAddress = address.map(_.max).max
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val minAlignment = address.map(_.alignment).min
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val minAlignment = address.map(_.alignment).min
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// The device had better not support a transfer larger than it's alignment
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// The device had better not support a transfer larger than its alignment
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require (minAlignment >= maxTransfer)
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require (minAlignment >= maxTransfer,
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s"minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)")
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}
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}
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case class AXI4SlavePortParameters(
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case class AXI4SlavePortParameters(
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@ -41,9 +42,12 @@ case class AXI4SlavePortParameters(
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val maxAddress = slaves.map(_.maxAddress).max
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val maxAddress = slaves.map(_.maxAddress).max
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// Check the link is not pointlessly wide
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// Check the link is not pointlessly wide
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require (maxTransfer >= beatBytes)
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require (maxTransfer >= beatBytes,
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s"maxTransfer ($maxTransfer) should not be smaller than bus width ($beatBytes)")
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// Check that the link can be implemented in AXI4
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// Check that the link can be implemented in AXI4
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require (maxTransfer <= beatBytes * (1 << AXI4Parameters.lenBits))
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val limit = beatBytes * (1 << AXI4Parameters.lenBits)
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require (maxTransfer <= limit,
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s"maxTransfer ($maxTransfer) cannot be larger than $limit on a $beatBytes*8 width bus")
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lazy val routingMask = AddressDecoder(slaves.map(_.address))
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lazy val routingMask = AddressDecoder(slaves.map(_.address))
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def findSafe(address: UInt) = Vec(slaves.map(_.address.map(_.contains(address)).reduce(_ || _)))
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def findSafe(address: UInt) = Vec(slaves.map(_.address.map(_.contains(address)).reduce(_ || _)))
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@ -52,7 +56,7 @@ case class AXI4SlavePortParameters(
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// Require disjoint ranges for addresses
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// Require disjoint ranges for addresses
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slaves.combinations(2).foreach { case Seq(x,y) =>
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slaves.combinations(2).foreach { case Seq(x,y) =>
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x.address.foreach { a => y.address.foreach { b =>
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x.address.foreach { a => y.address.foreach { b =>
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require (!a.overlaps(b))
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require (!a.overlaps(b), s"$a and $b overlap")
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} }
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} }
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}
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}
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}
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}
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@ -71,7 +75,7 @@ case class AXI4MasterPortParameters(
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val endId = masters.map(_.id.end).max
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val endId = masters.map(_.id.end).max
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// Require disjoint ranges for ids
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// Require disjoint ranges for ids
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masters.combinations(2).foreach { case Seq(x,y) => require (!x.id.overlaps(y.id)) }
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masters.combinations(2).foreach { case Seq(x,y) => require (!x.id.overlaps(y.id), s"$x and $y overlap") }
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}
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}
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case class AXI4BundleParameters(
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case class AXI4BundleParameters(
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@ -79,10 +83,10 @@ case class AXI4BundleParameters(
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dataBits: Int,
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dataBits: Int,
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idBits: Int)
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idBits: Int)
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{
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{
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require (dataBits >= 8)
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require (dataBits >= 8, s"AXI4 data bits must be >= 8 (got $dataBits)")
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require (addrBits >= 1)
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require (addrBits >= 1, s"AXI4 addr bits must be >= 1 (got $addrBits)")
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require (idBits >= 1)
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require (idBits >= 1, s"AXI4 id bits must be >= 1 (got $idBits)")
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require (isPow2(dataBits))
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require (isPow2(dataBits), s"AXI4 data bits must be pow2 (got $dataBits)")
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// Bring the globals into scope
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// Bring the globals into scope
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val lenBits = AXI4Parameters.lenBits
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val lenBits = AXI4Parameters.lenBits
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@ -41,8 +41,8 @@ case class TLManagerParameters(
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require ((regionType == RegionType.CACHED || regionType == RegionType.TRACKED) != supportsAcquireB.none)
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require ((regionType == RegionType.CACHED || regionType == RegionType.TRACKED) != supportsAcquireB.none)
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require (regionType != RegionType.UNCACHED || supportsGet)
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require (regionType != RegionType.UNCACHED || supportsGet)
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// Largest support transfer of all types
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val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
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val maxTransfer = List(
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val maxTransfer = List( // Largest supported transfer of all types
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supportsAcquireT.max,
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supportsAcquireT.max,
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supportsAcquireB.max,
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supportsAcquireB.max,
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supportsArithmetic.max,
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supportsArithmetic.max,
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@ -51,12 +51,10 @@ case class TLManagerParameters(
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supportsPutFull.max,
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supportsPutFull.max,
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supportsPutPartial.max).max
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supportsPutPartial.max).max
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val maxAddress = address.map(_.max).max
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val maxAddress = address.map(_.max).max
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val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
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// The device had better not support a transfer larger than it's alignment
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val minAlignment = address.map(_.alignment).min
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val minAlignment = address.map(_.alignment).min
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require (minAlignment >= maxTransfer, "minAlignment (" + minAlignment + ") must be >= maxTransfer (" + maxTransfer + ")")
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// The device had better not support a transfer larger than its alignment
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require (minAlignment >= maxTransfer, s"minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)")
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def toResource: ResourceAddress = {
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def toResource: ResourceAddress = {
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ResourceAddress(address,
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ResourceAddress(address,
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