TLBuffer: move TLBufferParams to diplomacy.BufferParams
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778c8a5c97
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ca2c709d29
@ -219,3 +219,20 @@ object AddressSet
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if (out.size != n) unify(out) else out.toList
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}
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}
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case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
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{
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require (depth >= 0)
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def isDefined = depth > 0
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def latency = if (isDefined && !flow) 1 else 0
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}
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object BufferParams
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{
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implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
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val default = BufferParams(2)
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val none = BufferParams(0)
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val flow = BufferParams(1, true, false)
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val pipe = BufferParams(1, false, true)
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}
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@ -49,7 +49,7 @@ class AHBFuzzMaster(aFlow: Boolean)(implicit p: Parameters) extends LazyModule
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node :=
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TLToAHB(aFlow)(
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TLDelayer(0.2)(
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TLBuffer(TLBufferParams.flow)(
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TLBuffer(BufferParams.flow)(
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TLDelayer(0.2)(
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model.node))))
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@ -71,7 +71,7 @@ class AHBFuzzSlave()(implicit p: Parameters) extends LazyModule
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ram.node :=
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TLFragmenter(4, 16)(
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TLDelayer(0.2)(
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TLBuffer(TLBufferParams.flow)(
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TLBuffer(BufferParams.flow)(
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TLDelayer(0.2)(
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AHBToTL()(
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node)))))
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@ -30,7 +30,7 @@ class APBFuzzBridge()(implicit p: Parameters) extends LazyModule
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xbar.node :=
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TLToAPB()(
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TLDelayer(0.2)(
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TLBuffer(TLBufferParams.flow)(
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TLBuffer(BufferParams.flow)(
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TLDelayer(0.2)(
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model.node))))
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@ -25,7 +25,7 @@ class AXI4LiteFuzzRAM()(implicit p: Parameters) extends LazyModule
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val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff)))
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model.node := fuzz.node
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xbar.node := TLDelayer(0.1)(TLBuffer(TLBufferParams.flow)(TLDelayer(0.2)(model.node)))
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xbar.node := TLDelayer(0.1)(TLBuffer(BufferParams.flow)(TLDelayer(0.2)(model.node)))
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ram.node := AXI4Fragmenter(lite=true)(TLToAXI4(0, true )(xbar.node))
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gpio.node := AXI4Fragmenter(lite=true)(TLToAXI4(0, false)(xbar.node))
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@ -48,7 +48,7 @@ class AXI4FullFuzzRAM()(implicit p: Parameters) extends LazyModule
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val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff)))
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model.node := fuzz.node
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xbar.node := TLDelayer(0.1)(TLBuffer(TLBufferParams.flow)(TLDelayer(0.2)(model.node)))
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xbar.node := TLDelayer(0.1)(TLBuffer(BufferParams.flow)(TLDelayer(0.2)(model.node)))
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ram.node := AXI4Fragmenter(lite=false, maxInFlight = 2)(TLToAXI4(4,false)(xbar.node))
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gpio.node := AXI4Fragmenter(lite=false, maxInFlight = 5)(TLToAXI4(4,true )(xbar.node))
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@ -72,7 +72,7 @@ class AXI4FuzzMaster()(implicit p: Parameters) extends LazyModule
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node :=
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TLToAXI4(4)(
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TLDelayer(0.1)(
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TLBuffer(TLBufferParams.flow)(
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TLBuffer(BufferParams.flow)(
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TLDelayer(0.1)(
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model.node))))
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@ -94,7 +94,7 @@ class AXI4FuzzSlave()(implicit p: Parameters) extends LazyModule
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ram.node :=
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TLFragmenter(4, 16)(
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TLDelayer(0.1)(
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TLBuffer(TLBufferParams.flow)(
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TLBuffer(BufferParams.flow)(
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TLDelayer(0.1)(
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AXI4ToTL()(
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AXI4Fragmenter()(
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@ -8,33 +8,16 @@ import config._
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import diplomacy._
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import scala.math.{min,max}
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case class TLBufferParams(depth: Int, flow: Boolean, pipe: Boolean)
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{
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require (depth >= 0)
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def isDefined = depth > 0
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def latency = if (isDefined && !flow) 1 else 0
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}
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object TLBufferParams
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{
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implicit def apply(depth: Int): TLBufferParams = TLBufferParams(depth, false, false)
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val default = TLBufferParams(2)
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val none = TLBufferParams(0)
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val flow = TLBufferParams(1, true, false)
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val pipe = TLBufferParams(1, false, true)
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}
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class TLBuffer(
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a: TLBufferParams,
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b: TLBufferParams,
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c: TLBufferParams,
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d: TLBufferParams,
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e: TLBufferParams)(implicit p: Parameters) extends LazyModule
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a: BufferParams,
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b: BufferParams,
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c: BufferParams,
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d: BufferParams,
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e: BufferParams)(implicit p: Parameters) extends LazyModule
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{
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def this(ace: TLBufferParams, bd: TLBufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
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def this(abcde: TLBufferParams)(implicit p: Parameters) = this(abcde, abcde)
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def this()(implicit p: Parameters) = this(TLBufferParams.default)
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def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
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def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
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def this()(implicit p: Parameters) = this(BufferParams.default)
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val node = TLAdapterNode(
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clientFn = { p => p.copy(minLatency = p.minLatency + b.latency + c.latency) },
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@ -46,7 +29,7 @@ class TLBuffer(
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val out = node.bundleOut
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}
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def buffer[T <: Data](config: TLBufferParams, data: DecoupledIO[T]): DecoupledIO[T] = {
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def buffer[T <: Data](config: BufferParams, data: DecoupledIO[T]): DecoupledIO[T] = {
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if (config.isDefined) {
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Queue(data, config.depth, pipe=config.pipe, flow=config.flow)
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} else {
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@ -77,15 +60,15 @@ class TLBuffer(
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object TLBuffer
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{
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// applied to the TL source node; y.node := TLBuffer(x.node)
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def apply() (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(TLBufferParams.default)(x)
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def apply(abcde: TLBufferParams) (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(abcde, abcde)(x)
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def apply(ace: TLBufferParams, bd: TLBufferParams)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(ace, bd, ace, bd, ace)(x)
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def apply() (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(BufferParams.default)(x)
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def apply(abcde: BufferParams) (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(abcde, abcde)(x)
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def apply(ace: BufferParams, bd: BufferParams)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(ace, bd, ace, bd, ace)(x)
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def apply(
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a: TLBufferParams,
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b: TLBufferParams,
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c: TLBufferParams,
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d: TLBufferParams,
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e: TLBufferParams)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
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a: BufferParams,
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b: BufferParams,
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c: BufferParams,
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d: BufferParams,
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e: BufferParams)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
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val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
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buffer.node := x
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buffer.node
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