TLBuffer: move TLBufferParams to diplomacy.BufferParams

src/main/scala/diplomacy/Parameters.scala

@@ -219,3 +219,20 @@ object AddressSet
     if (out.size != n) unify(out) else out.toList
   }
 }
+
+case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
+{
+  require (depth >= 0)
+  def isDefined = depth > 0
+  def latency = if (isDefined && !flow) 1 else 0
+}
+
+object BufferParams
+{
+  implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
+
+  val default = BufferParams(2)
+  val none    = BufferParams(0)
+  val flow    = BufferParams(1, true, false)
+  val pipe    = BufferParams(1, false, true)
+}

src/main/scala/uncore/ahb/Test.scala

@@ -49,7 +49,7 @@ class AHBFuzzMaster(aFlow: Boolean)(implicit p: Parameters) extends LazyModule
   node :=
     TLToAHB(aFlow)(
     TLDelayer(0.2)(
-    TLBuffer(TLBufferParams.flow)(
+    TLBuffer(BufferParams.flow)(
     TLDelayer(0.2)(
     model.node))))
 
@@ -71,7 +71,7 @@ class AHBFuzzSlave()(implicit p: Parameters) extends LazyModule
   ram.node :=
     TLFragmenter(4, 16)(
     TLDelayer(0.2)(
-    TLBuffer(TLBufferParams.flow)(
+    TLBuffer(BufferParams.flow)(
     TLDelayer(0.2)(
     AHBToTL()(
     node)))))

src/main/scala/uncore/apb/Test.scala

@@ -30,7 +30,7 @@ class APBFuzzBridge()(implicit p: Parameters) extends LazyModule
   xbar.node :=
     TLToAPB()(
     TLDelayer(0.2)(
-    TLBuffer(TLBufferParams.flow)(
+    TLBuffer(BufferParams.flow)(
     TLDelayer(0.2)(
     model.node))))
 

src/main/scala/uncore/axi4/Test.scala

@@ -25,7 +25,7 @@ class AXI4LiteFuzzRAM()(implicit p: Parameters) extends LazyModule
   val ram   = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff)))
 
   model.node := fuzz.node
-  xbar.node  := TLDelayer(0.1)(TLBuffer(TLBufferParams.flow)(TLDelayer(0.2)(model.node)))
+  xbar.node  := TLDelayer(0.1)(TLBuffer(BufferParams.flow)(TLDelayer(0.2)(model.node)))
   ram.node   := AXI4Fragmenter(lite=true)(TLToAXI4(0, true )(xbar.node))
   gpio.node  := AXI4Fragmenter(lite=true)(TLToAXI4(0, false)(xbar.node))
 
@@ -48,7 +48,7 @@ class AXI4FullFuzzRAM()(implicit p: Parameters) extends LazyModule
   val ram   = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff)))
 
   model.node := fuzz.node
-  xbar.node  := TLDelayer(0.1)(TLBuffer(TLBufferParams.flow)(TLDelayer(0.2)(model.node)))
+  xbar.node  := TLDelayer(0.1)(TLBuffer(BufferParams.flow)(TLDelayer(0.2)(model.node)))
   ram.node   := AXI4Fragmenter(lite=false, maxInFlight = 2)(TLToAXI4(4,false)(xbar.node))
   gpio.node  := AXI4Fragmenter(lite=false, maxInFlight = 5)(TLToAXI4(4,true )(xbar.node))
 
@@ -72,7 +72,7 @@ class AXI4FuzzMaster()(implicit p: Parameters) extends LazyModule
   node :=
     TLToAXI4(4)(
     TLDelayer(0.1)(
-    TLBuffer(TLBufferParams.flow)(
+    TLBuffer(BufferParams.flow)(
     TLDelayer(0.1)(
     model.node))))
 
@@ -94,7 +94,7 @@ class AXI4FuzzSlave()(implicit p: Parameters) extends LazyModule
   ram.node :=
     TLFragmenter(4, 16)(
     TLDelayer(0.1)(
-    TLBuffer(TLBufferParams.flow)(
+    TLBuffer(BufferParams.flow)(
     TLDelayer(0.1)(
     AXI4ToTL()(
     AXI4Fragmenter()(

src/main/scala/uncore/tilelink2/Buffer.scala

@@ -8,33 +8,16 @@ import config._
 import diplomacy._
 import scala.math.{min,max}
 
-case class TLBufferParams(depth: Int, flow: Boolean, pipe: Boolean)
-{
-  require (depth >= 0)
-  def isDefined = depth > 0
-  def latency = if (isDefined && !flow) 1 else 0
-}
-
-object TLBufferParams
-{
-  implicit def apply(depth: Int): TLBufferParams = TLBufferParams(depth, false, false)
-
-  val default = TLBufferParams(2)
-  val none    = TLBufferParams(0)
-  val flow    = TLBufferParams(1, true, false)
-  val pipe    = TLBufferParams(1, false, true)
-}
-
 class TLBuffer(
-  a: TLBufferParams,
+  a: BufferParams,
-  b: TLBufferParams,
+  b: BufferParams,
-  c: TLBufferParams,
+  c: BufferParams,
-  d: TLBufferParams,
+  d: BufferParams,
-  e: TLBufferParams)(implicit p: Parameters) extends LazyModule
+  e: BufferParams)(implicit p: Parameters) extends LazyModule
 {
-  def this(ace: TLBufferParams, bd: TLBufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
+  def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
-  def this(abcde: TLBufferParams)(implicit p: Parameters) = this(abcde, abcde)
+  def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
-  def this()(implicit p: Parameters) = this(TLBufferParams.default)
+  def this()(implicit p: Parameters) = this(BufferParams.default)
 
   val node = TLAdapterNode(
     clientFn  = { p => p.copy(minLatency = p.minLatency + b.latency + c.latency) },
@@ -46,7 +29,7 @@ class TLBuffer(
       val out = node.bundleOut
     }
 
-    def buffer[T <: Data](config: TLBufferParams, data: DecoupledIO[T]): DecoupledIO[T] = {
+    def buffer[T <: Data](config: BufferParams, data: DecoupledIO[T]): DecoupledIO[T] = {
       if (config.isDefined) {
         Queue(data, config.depth, pipe=config.pipe, flow=config.flow)
       } else {
@@ -77,15 +60,15 @@ class TLBuffer(
 object TLBuffer
 {
   // applied to the TL source node; y.node := TLBuffer(x.node)
-  def apply()                                       (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(TLBufferParams.default)(x)
+  def apply()                                   (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(BufferParams.default)(x)
-  def apply(abcde: TLBufferParams)                  (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(abcde, abcde)(x)
+  def apply(abcde: BufferParams)                (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(abcde, abcde)(x)
-  def apply(ace: TLBufferParams, bd: TLBufferParams)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(ace, bd, ace, bd, ace)(x)
+  def apply(ace: BufferParams, bd: BufferParams)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(ace, bd, ace, bd, ace)(x)
   def apply(
-      a: TLBufferParams,
+      a: BufferParams,
-      b: TLBufferParams,
+      b: BufferParams,
-      c: TLBufferParams,
+      c: BufferParams,
-      d: TLBufferParams,
+      d: BufferParams,
-      e: TLBufferParams)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
+      e: BufferParams)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
     val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
     buffer.node := x
     buffer.node