riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

rocket,Rocket: fix type mismatch (#819)

Browse Source
This commit is contained in:
Zihao Yu
2017-06-28 02:22:08 +08:00
committed by Andrew Waterman
parent 8d07d0af38
commit c9cfe46604
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/rocket/Rocket.scala
View File

@@ -643,7 +643,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
if (enableCommitLog) {
val pc = Wire(SInt(width=xLen))
pc := wb_reg_pc
pc := wb_reg_pc.asSInt
val inst = wb_reg_inst
val rd = RegNext(RegNext(RegNext(id_waddr)))
val wfd = wb_ctrl.wfd