riscv/rocket-chip
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rocket,Rocket: fix type mismatch (#819)

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Zihao Yu 2017-06-28 02:22:08 +08:00 committed by Andrew Waterman
parent 8d07d0af38
commit c9cfe46604
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocket/Rocket.scala
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@ -643,7 +643,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
if (enableCommitLog) { if (enableCommitLog) {
val pc = Wire(SInt(width=xLen)) val pc = Wire(SInt(width=xLen))
pc := wb_reg_pc pc := wb_reg_pc.asSInt
val inst = wb_reg_inst val inst = wb_reg_inst
val rd = RegNext(RegNext(RegNext(id_waddr))) val rd = RegNext(RegNext(RegNext(id_waddr)))
val wfd = wb_ctrl.wfd val wfd = wb_ctrl.wfd