riscv/rocket-chip
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Only report D$ exceptions on not-nacked accesses

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Andrew Waterman 2017-04-17 22:42:16 -07:00 committed by Andrew Waterman
parent 5934c7b4b9
commit c99ce7ce5d
2 changed files with 6 additions and 2 deletions
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4
src/main/scala/rocket/DCache.scala
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@ -103,7 +103,6 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
// address translation // address translation
val tlb = Module(new TLB(log2Ceil(coreDataBytes), nTLBEntries)) val tlb = Module(new TLB(log2Ceil(coreDataBytes), nTLBEntries))
io.ptw <> tlb.io.ptw io.ptw <> tlb.io.ptw
io.cpu.s2_xcpt := RegEnable(Mux(tlb.io.req.valid && !tlb.io.resp.miss, tlb.io.resp, 0.U.asTypeOf(tlb.io.resp)), s1_valid_not_nacked)
tlb.io.req.valid := s1_valid && !io.cpu.s1_kill && (s1_readwrite || s1_sfence) tlb.io.req.valid := s1_valid && !io.cpu.s1_kill && (s1_readwrite || s1_sfence)
tlb.io.req.bits.sfence.valid := s1_sfence tlb.io.req.bits.sfence.valid := s1_sfence
tlb.io.req.bits.sfence.bits.rs1 := s1_req.typ(0) tlb.io.req.bits.sfence.bits.rs1 := s1_req.typ(0)
@ -481,6 +480,9 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
io.cpu.resp.bits.replay := false io.cpu.resp.bits.replay := false
io.cpu.ordered := !(s1_valid || s2_valid || cached_grant_wait || uncachedInFlight.asUInt.orR) io.cpu.ordered := !(s1_valid || s2_valid || cached_grant_wait || uncachedInFlight.asUInt.orR)
val s1_xcpt = Mux(s1_nack || !tlb.io.req.valid, 0.U.asTypeOf(tlb.io.resp), tlb.io.resp)
io.cpu.s2_xcpt := RegEnable(s1_xcpt, s1_valid)
// uncached response // uncached response
io.cpu.replay_next := tl_out.d.fire() && grantIsUncachedData io.cpu.replay_next := tl_out.d.fire() && grantIsUncachedData
val doUncachedResp = Reg(next = io.cpu.replay_next) val doUncachedResp = Reg(next = io.cpu.replay_next)

4
src/main/scala/rocket/NBDcache.scala
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@ -699,7 +699,6 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
val dtlb = Module(new TLB(log2Ceil(coreDataBytes), nTLBEntries)) val dtlb = Module(new TLB(log2Ceil(coreDataBytes), nTLBEntries))
io.ptw <> dtlb.io.ptw io.ptw <> dtlb.io.ptw
io.cpu.s2_xcpt := RegEnable(Mux(dtlb.io.req.valid && !dtlb.io.resp.miss, dtlb.io.resp, 0.U.asTypeOf(dtlb.io.resp)), s1_clk_en)
dtlb.io.req.valid := s1_valid && !io.cpu.s1_kill && (s1_readwrite || s1_sfence) dtlb.io.req.valid := s1_valid && !io.cpu.s1_kill && (s1_readwrite || s1_sfence)
dtlb.io.req.bits.sfence.valid := s1_sfence dtlb.io.req.bits.sfence.valid := s1_sfence
dtlb.io.req.bits.sfence.bits.rs1 := s1_req.typ(0) dtlb.io.req.bits.sfence.bits.rs1 := s1_req.typ(0)
@ -976,6 +975,9 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
io.cpu.ordered := mshrs.io.fence_rdy && !s1_valid && !s2_valid io.cpu.ordered := mshrs.io.fence_rdy && !s1_valid && !s2_valid
io.cpu.replay_next := (s1_replay && s1_read) || mshrs.io.replay_next io.cpu.replay_next := (s1_replay && s1_read) || mshrs.io.replay_next
val s1_xcpt = Mux(s1_nack || !dtlb.io.req.valid, 0.U.asTypeOf(dtlb.io.resp), dtlb.io.resp)
io.cpu.s2_xcpt := RegEnable(s1_xcpt, s1_clk_en)
// performance events // performance events
io.cpu.acquire := edge.done(tl_out.a) io.cpu.acquire := edge.done(tl_out.a)
io.cpu.release := edge.done(tl_out.c) io.cpu.release := edge.done(tl_out.c)