riscv/rocket-chip
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Only report D$ exceptions on not-nacked accesses

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This commit is contained in:
Andrew Waterman
2017-04-17 22:42:16 -07:00
committed by Andrew Waterman
parent 5934c7b4b9
commit c99ce7ce5d
2 changed files with 6 additions and 2 deletions
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4
src/main/scala/rocket/NBDcache.scala
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@ -699,7 +699,6 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
val dtlb = Module(new TLB(log2Ceil(coreDataBytes), nTLBEntries))
io.ptw <> dtlb.io.ptw
io.cpu.s2_xcpt := RegEnable(Mux(dtlb.io.req.valid && !dtlb.io.resp.miss, dtlb.io.resp, 0.U.asTypeOf(dtlb.io.resp)), s1_clk_en)
dtlb.io.req.valid := s1_valid && !io.cpu.s1_kill && (s1_readwrite || s1_sfence)
dtlb.io.req.bits.sfence.valid := s1_sfence
dtlb.io.req.bits.sfence.bits.rs1 := s1_req.typ(0)
@ -976,6 +975,9 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
io.cpu.ordered := mshrs.io.fence_rdy && !s1_valid && !s2_valid
io.cpu.replay_next := (s1_replay && s1_read) || mshrs.io.replay_next
val s1_xcpt = Mux(s1_nack || !dtlb.io.req.valid, 0.U.asTypeOf(dtlb.io.resp), dtlb.io.resp)
io.cpu.s2_xcpt := RegEnable(s1_xcpt, s1_clk_en)
// performance events
io.cpu.acquire := edge.done(tl_out.a)
io.cpu.release := edge.done(tl_out.c)