riscv/rocket-chip
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buses: Name all the things.

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This commit is contained in:
Megan Wachs 2017-08-30 16:21:08 -07:00
parent 32cb358c81
commit c99afe4c66
6 changed files with 36 additions and 24 deletions
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5
src/main/scala/coreplex/FrontBus.scala
View File

@ -17,15 +17,14 @@ case class FrontBusParams(
case object FrontBusParams extends Field[FrontBusParams]
class FrontBus(params: FrontBusParams)(implicit p: Parameters) extends TLBusWrapper(params) {
xbar.suggestName("FrontBus")
class FrontBus(params: FrontBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "FrontBus") {
def fromSyncMasters(params: BufferParams = BufferParams.default, buffers: Int = 1, name: Option[String] = None): TLInwardNode =
fromSyncPorts(params, buffers, name)
def fromSyncPorts(params: BufferParams = BufferParams.default, buffers: Int = 1, name: Option[String] = None): TLInwardNode = {
val buf = List.fill(buffers)(LazyModule(new TLBuffer(params)))
name.foreach { n => buf.zipWithIndex foreach {case (b, i) => b.suggestName(s"FrontBus_${n}_${i}_TLBuffer")}}
name.foreach { n => buf.zipWithIndex foreach {case (b, i) => b.suggestName(s"${busName}_${n}_${i}_TLBuffer")}}
for(i<-1 until buffers) {
buf(i).node :=* buf(i-1).node
}

3
src/main/scala/coreplex/MemoryBus.scala
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@ -43,8 +43,7 @@ case class MemoryBusParams(
case object MemoryBusParams extends Field[MemoryBusParams]
/** Wrapper for creating TL nodes from a bus connected to the back of each mem channel */
class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWrapper(params)(p) {
xbar.suggestName("MemoryBus")
class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "MemoryBus")(p) {
def fromCoherenceManager: TLInwardNode = inwardBufNode
def toDRAMController: TLOutwardNode = outwardBufNode

3
src/main/scala/coreplex/PeripheryBus.scala
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@ -21,8 +21,7 @@ case class PeripheryBusParams(
case object PeripheryBusParams extends Field[PeripheryBusParams]
class PeripheryBus(params: PeripheryBusParams)(implicit p: Parameters) extends TLBusWrapper(params) {
xbar.suggestName("PeripheryBus")
class PeripheryBus(params: PeripheryBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "PeripheryBus") {
def toFixedWidthSingleBeatSlave(widthBytes: Int) = {
TLFragmenter(widthBytes, params.blockBytes)(outwardWWNode)

2
src/main/scala/coreplex/RocketCoreplex.scala
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@ -52,7 +52,7 @@ trait HasRocketTiles extends HasSystemBus
case AsynchronousCrossing(depth, sync) => {
val wrapper = LazyModule(new AsyncRocketTile(c, i)(pWithExtra))
sbus.fromAsyncTiles(depth, sync) :=* wrapper.masterNode
wrapper.slaveNode :*= pbus.toAsyncSlaves(sync)(c.name)
wrapper.slaveNode :*= pbus.toAsyncSlaves(sync, c.name)
wrapper
}
case RationalCrossing(direction) => {

20
src/main/scala/coreplex/SystemBus.scala
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@ -17,10 +17,10 @@ case class SystemBusParams(
case object SystemBusParams extends Field[SystemBusParams]
class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWrapper(params) {
xbar.suggestName("SystemBus")
class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "SystemBus") {
private val master_splitter = LazyModule(new TLSplitter) // Allows cycle-free connection to external networks
master_splitter.suggestName(s"${busName}_master_TLSplitter"}
inwardNode :=* master_splitter.node
def busView = master_splitter.node.edgesIn.head
@ -28,8 +28,12 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
protected def outwardSplitNode: TLOutwardNode = master_splitter.node
private val tile_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
tile_fixer.suggestName(s"${busName}_tile_TLFIFOFixer")
private val port_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
port_fixer.suggestName(s"${busName}_port_TLFIFOFixer")
private val pbus_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
pbus_fixer.suggestName(s"${busName}_pbus_TLFIFOFixer")
master_splitter.node :=* tile_fixer.node
master_splitter.node :=* port_fixer.node
pbus_fixer.node :*= outwardWWNode
@ -54,28 +58,28 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
def fromSyncTiles(params: BufferParams, name: Option[String] = None): TLInwardNode = {
val buf = LazyModule(new TLBuffer(params))
name.foreach{n => buf.suggestName(s"SystemBus_${n}_TLBuffer")}
name.foreach{n => buf.suggestName(s"${busName}_${n}_TLBuffer")}
tile_fixer.node :=* buf.node
buf.node
}
def fromRationalTiles(dir: RationalDirection, name: Option[String] = None): TLRationalInwardNode = {
val sink = LazyModule(new TLRationalCrossingSink(direction = dir))
name.foreach{n => sink.suggestName(s"SystemBus_${n}_TLRationalCrossingSink")}
name.foreach{n => sink.suggestName(s"${busName}_${n}_TLRationalCrossingSink")}
tile_fixer.node :=* sink.node
sink.node
}
def fromAsyncTiles(depth: Int, sync: Int, name: Option[String] = None): TLAsyncInwardNode = {
val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
name.foreach{n => sink.suggestName(s"SystemBus_${n}_TLAsyncCrossingSink")}
name.foreach{n => sink.suggestName(s"${busName}_${n}_TLAsyncCrossignSink")}
tile_fixer.node :=* sink.node
sink.node
}
def fromSyncPorts(params: BufferParams = BufferParams.default, name: Option[String] = None): TLInwardNode = {
val buffer = LazyModule(new TLBuffer(params))
name.foreach{ n => buffer.suggestName(s"SystemBus_${n}_TLBuffer") }
name.foreach{ n => buffer.suggestName(s"${busName}_${n}_TLBuffer") }
port_fixer.node :=* buffer.node
buffer.node
}
@ -86,7 +90,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
def fromAsyncPorts(depth: Int = 8, sync: Int = 3, name : Option[String] = None): TLAsyncInwardNode = {
val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
name.foreach{ n => sink.suggestName(s"SystemBus_${n}_TLAsyncCrossingSink") }
name.foreach{ n => sink.suggestName(s"${busName}_${n}_TLAsyncCrossingSink") }
port_fixer.node :=* sink.node
sink.node
}
@ -95,7 +99,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
def fromRationalPorts(dir: RationalDirection, name: Option[String] = None): TLRationalInwardNode = {
val sink = LazyModule(new TLRationalCrossingSink(dir))
name.foreach{ n => sink.suggestName(s"SystemBus_${n}_TLRationalCrossingSink") }
name.foreach{ n => sink.suggestName(s"${busName}_${n}_TLRationalCrossingSink") }
port_fixer.node :=* sink.node
sink.node
}

27
src/main/scala/tilelink/Bus.scala
View File

@ -21,7 +21,8 @@ trait TLBusParams {
def blockOffset: Int = log2Up(blockBytes)
}
abstract class TLBusWrapper(params: TLBusParams)(implicit p: Parameters) extends TLBusParams {
abstract class TLBusWrapper(params: TLBusParams, val busName: String)(implicit p: Parameters) extends TLBusParams {
val beatBytes = params.beatBytes
val blockBytes = params.blockBytes
val masterBuffering = params.masterBuffering
@ -30,10 +31,16 @@ abstract class TLBusWrapper(params: TLBusParams)(implicit p: Parameters) extends
private val delayProb = p(TLBusDelayProbability)
protected val xbar = LazyModule(new TLXbar)
xbar.suggestName(busName)
private val master_buffer = LazyModule(new TLBuffer(masterBuffering))
master_buffer.suggestName(s"${busName}_master_TLBuffer")
private val slave_buffer = LazyModule(new TLBuffer(slaveBuffering))
slave_buffer.suggestName(s"${busName}_slave_TLBuffer")
private val slave_frag = LazyModule(new TLFragmenter(beatBytes, blockBytes))
slave_frag.suggestName(s"${busName}_slave_TLFragmenter")
private val slave_ww = LazyModule(new TLWidthWidget(beatBytes))
slave_ww.suggestName(s"${busName}_slave_TLWidthWidget")
private val delayedNode = if (delayProb > 0.0) {
val firstDelay = LazyModule(new TLDelayer(delayProb))
@ -63,44 +70,48 @@ abstract class TLBusWrapper(params: TLBusParams)(implicit p: Parameters) extends
def bufferToSlaves: TLOutwardNode = outwardBufNode
def toAsyncSlaves(sync: Int = 3)(name: Option[String] = None): TLAsyncOutwardNode = {
def toAsyncSlaves(sync: Int = 3, name: Option[String] = None): TLAsyncOutwardNode = {
val source = LazyModule(new TLAsyncCrossingSource(sync))
name.foreach(source.suggestName)
name.foreach{ n => source.suggestName(s"${busName}_${n}_TLAsyncCrossingSource")}
source.node :*= outwardNode
source.node
}
def toRationalSlaves(name: Option[String] = None): TLRationalOutwardNode = {
val source = LazyModule(new TLRationalCrossingSource())
name.foreach(source.suggestName)
name.foreach{ n => source.suggestName(s"${busName}_${n}_TLRationalCrossingSource")}
source.node :*= outwardNode
source.node
}
def toVariableWidthSlaves: TLOutwardNode = outwardFragNode
def toAsyncVariableWidthSlaves(sync: Int = 3): TLAsyncOutwardNode = {
def toAsyncVariableWidthSlaves(sync: Int = 3, name: Option[String] = None): TLAsyncOutwardNode = {
val source = LazyModule(new TLAsyncCrossingSource(sync))
name.foreach {n => source.suggestName(s"${busName}_${name}_TLAsyncCrossingSource")}
source.node :*= outwardFragNode
source.node
}
def toRationalVariableWidthSlaves: TLRationalOutwardNode = {
def toRationalVariableWidthSlaves(name: Option[String] = None): TLRationalOutwardNode = {
val source = LazyModule(new TLRationalCrossingSource())
name.foreach {n => source.suggestName(s"${busName}_${name}_TLRationalCrossingSource")}
source.node :*= outwardFragNode
source.node
}
def toFixedWidthSlaves: TLOutwardNode = outwardWWNode
def toAsyncFixedWidthSlaves(sync: Int = 3): TLAsyncOutwardNode = {
def toAsyncFixedWidthSlaves(sync: Int = 3, name: Option[String] = None): TLAsyncOutwardNode = {
val source = LazyModule(new TLAsyncCrossingSource(sync))
name.foreach { n => source.suggestName(s"${busName}_${name}_TLAsyncCrossingSource")}
source.node := outwardWWNode
source.node
}
def toRationalFixedWidthSlaves: TLRationalOutwardNode = {
def toRationalFixedWidthSlaves(name: Option[String] = None): TLRationalOutwardNode = {
val source = LazyModule(new TLRationalCrossingSource())
name.foreach {n => source.suggestName(s"${busName}_${name}_TLRationalCrossingSource")}
source.node :*= outwardWWNode
source.node
}