riscv/rocket-chip
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buses: Name all the things.

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This commit is contained in:
Megan Wachs
2017-08-30 16:21:08 -07:00
parent 32cb358c81
commit c99afe4c66
6 changed files with 36 additions and 24 deletions
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3
src/main/scala/coreplex/PeripheryBus.scala
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@ -21,8 +21,7 @@ case class PeripheryBusParams(
case object PeripheryBusParams extends Field[PeripheryBusParams]
class PeripheryBus(params: PeripheryBusParams)(implicit p: Parameters) extends TLBusWrapper(params) {
xbar.suggestName("PeripheryBus")
class PeripheryBus(params: PeripheryBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "PeripheryBus") {
def toFixedWidthSingleBeatSlave(widthBytes: Int) = {
TLFragmenter(widthBytes, params.blockBytes)(outwardWWNode)