riscv/rocket-chip
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turn off DRAMSideLLC

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Yunsup Lee
2014-09-11 22:10:25 -07:00
parent b5a64487eb
commit c98afa1fea
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/PublicConfigs.scala
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@@ -103,7 +103,7 @@ class DefaultConfig extends ChiselConfig {
if(site[Boolean]("USE_DRAMSIDE_LLC")) { if(site[Boolean]("USE_DRAMSIDE_LLC")) {
val tag = Mem(Bits(width = 152), 512, seqRead = true) val tag = Mem(Bits(width = 152), 512, seqRead = true)
val data = Mem(Bits(width = 64), 4096, seqRead = true) val data = Mem(Bits(width = 64), 4096, seqRead = true)
Module(new DRAMSideLLC(sets=512, ways=8, outstanding=16, Module(new DRAMSideLLC_HasKnownBug(sets=512, ways=8, outstanding=16,
refill_cycles=refill, tagLeaf=tag, dataLeaf=data)) refill_cycles=refill, tagLeaf=tag, dataLeaf=data))
} else { } else {
Module(new DRAMSideLLCNull(8, refill)) Module(new DRAMSideLLCNull(8, refill))
@@ -130,7 +130,7 @@ class DefaultConfig extends ChiselConfig {
} }
case "ENABLE_SHARING" => true case "ENABLE_SHARING" => true
case "ENABLE_CLEAN_EXCLUSIVE" => true case "ENABLE_CLEAN_EXCLUSIVE" => true
case "USE_DRAMSIDE_LLC" => false case "USE_DRAMSIDE_LLC" => false // DO NOT TURN ON. Read uncore/src/main/scala/llc.scala
case "USE_L2_CACHE" => false case "USE_L2_CACHE" => false
} }
} }