riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

New virtual memory implementation (Sv39)

Browse Source
This commit is contained in:
Andrew Waterman 2015-03-27 16:21:29 -07:00
parent 8959b2e81a
commit c941f0a68e
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
uncore/src/main/scala/memserdes.scala
View File

@ -7,8 +7,9 @@ import scala.math._
case object PAddrBits extends Field[Int] case object PAddrBits extends Field[Int]
case object VAddrBits extends Field[Int] case object VAddrBits extends Field[Int]
case object PgIdxBits extends Field[Int] case object PgIdxBits extends Field[Int]
case object PgLevels extends Field[Int]
case object PgLevelBits extends Field[Int]
case object ASIdBits extends Field[Int] case object ASIdBits extends Field[Int]
case object PermBits extends Field[Int]
case object PPNBits extends Field[Int] case object PPNBits extends Field[Int]
case object VPNBits extends Field[Int] case object VPNBits extends Field[Int]