riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

fixing bufferless broadcast hub

Browse Source
This commit is contained in:
Howard Mao
2016-07-04 17:07:58 -07:00
parent af51b6f363
commit c924ec2a22
5 changed files with 27 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
src/main/scala/Configs.scala
View File

@ -366,6 +366,14 @@ class WithL2Cache extends Config(
knobValues = { case "L2_WAYS" => 8; case "L2_CAPACITY_IN_KB" => 2048; case "L2_SPLIT_METADATA" => false; case _ => throw new CDEMatchError }
)
class WithBufferlessBroadcastHub extends Config(
(pname, site, here) => pname match {
case BuildL2CoherenceManager => (id: Int, p: Parameters) =>
Module(new BufferlessBroadcastHub()(p.alterPartial({
case InnerTLId => "L1toL2"
case OuterTLId => "L2toMC" })))
})
class WithPLRU extends Config(
(pname, site, here) => pname match {
case L2Replacer => () => new SeqPLRU(site(NSets), site(NWays))
@ -388,6 +396,9 @@ class DefaultL2Config extends Config(new WithL2Cache ++ new BaseConfig)
class DefaultL2FPGAConfig extends Config(
new WithL2Capacity(64) ++ new WithL2Cache ++ new DefaultFPGAConfig)
class DefaultBufferlessConfig extends Config(
new WithBufferlessBroadcastHub ++ new BaseConfig)
class PLRUL2Config extends Config(new WithPLRU ++ new DefaultL2Config)
class WithRV32 extends Config(