riscv/rocket-chip
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base NGenerators on NTiles, not the other way around

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This commit is contained in:
Howard Mao 2015-12-01 15:26:09 -08:00
parent e4043570bd
commit c8c68e75bb
1 changed files with 3 additions and 5 deletions
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8
src/main/scala/Configs.scala
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@ -313,15 +313,13 @@ class WithGroundTest extends Config(
class WithMemtest extends Config( class WithMemtest extends Config(
(pname, site, here) => pname match { (pname, site, here) => pname match {
case NGenerators => 1 case NGenerators => site(NTiles)
case GenerateUncached => true case GenerateUncached => true
case GenerateCached => true case GenerateCached => true
case MaxGenerateRequests => 128 case MaxGenerateRequests => 128
case GeneratorStartAddress => 0 case GeneratorStartAddress => 0
case BuildGroundTest => case BuildGroundTest =>
(id: Int, p: Parameters) => Module(new GeneratorTest(id)(p)) (id: Int, p: Parameters) => Module(new GeneratorTest(id)(p))
case NTiles => site(NGenerators)
}) })
class WithCacheFillTest extends Config( class WithCacheFillTest extends Config(
@ -383,8 +381,8 @@ class DualChannelDualBankL2Config extends Config(
new With2MemoryChannels ++ new With2BanksPerMemChannel ++ new With2MemoryChannels ++ new With2BanksPerMemChannel ++
new WithL2Cache ++ new DefaultConfig) new WithL2Cache ++ new DefaultConfig)
class MemtestDualChannelDualBankL2Config extends Config( class FancyMemtestConfig extends Config(
new With2MemoryChannels ++ new With2BanksPerMemChannel ++ new With2Cores ++ new With2MemoryChannels ++ new With2BanksPerMemChannel ++
new WithMemtest ++ new WithL2Cache ++ new GroundTestConfig) new WithMemtest ++ new WithL2Cache ++ new GroundTestConfig)
class WithRoccExample extends Config( class WithRoccExample extends Config(