riscv/rocket-chip
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minor btb cleanup

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This commit is contained in:
Andrew Waterman
2015-07-29 15:03:01 -07:00
parent a2fdcdcaef
commit c8c312e860
1 changed files with 3 additions and 2 deletions
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5
rocket/src/main/scala/btb.scala
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@@ -252,12 +252,13 @@ class BTB(updates_out_of_order: Boolean = false) extends Module with BTBParamete
if (nBHT > 0) { if (nBHT > 0) {
val bht = new BHT(nBHT) val bht = new BHT(nBHT)
val res = bht.get(io.req.bits.addr, io.req.valid && hits.orR && !Mux1H(hits, isJump)) val isBranch = !Mux1H(hits, isJump)
val res = bht.get(io.req.bits.addr, io.req.valid && io.resp.valid && isBranch)
val update_btb_hit = io.bht_update.bits.prediction.valid val update_btb_hit = io.bht_update.bits.prediction.valid
when (io.bht_update.valid && update_btb_hit) { when (io.bht_update.valid && update_btb_hit) {
bht.update(io.bht_update.bits.pc, io.bht_update.bits.prediction.bits.bht, io.bht_update.bits.taken, io.bht_update.bits.mispredict) bht.update(io.bht_update.bits.pc, io.bht_update.bits.prediction.bits.bht, io.bht_update.bits.taken, io.bht_update.bits.mispredict)
} }
when (!res.value(0) && !Mux1H(hits, isJump)) { io.resp.bits.taken := false } when (!res.value(0) && isBranch) { io.resp.bits.taken := false }
io.resp.bits.bht := res io.resp.bits.bht := res
} }