diff --git a/src/main/scala/uncore/ahb/Test.scala b/src/main/scala/uncore/ahb/Test.scala
index abfd4128..c294fca9 100644
--- a/src/main/scala/uncore/ahb/Test.scala
+++ b/src/main/scala/uncore/ahb/Test.scala
@@ -16,9 +16,9 @@ class RRTest1(address: BigInt)(implicit p: Parameters) extends AHBRegisterRouter
   new AHBRegBundle((), _)    with RRTest1Bundle)(
   new AHBRegModule((), _, _) with RRTest1Module)
 
-class AHBFuzzNative(aFlow: Boolean)(implicit p: Parameters) extends LazyModule
+class AHBFuzzNative(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends LazyModule
 {
-  val fuzz  = LazyModule(new TLFuzzer(5000))
+  val fuzz  = LazyModule(new TLFuzzer(txns))
   val model = LazyModule(new TLRAMModel("AHBFuzzNative"))
   var xbar  = LazyModule(new AHBFanout)
   val ram   = LazyModule(new AHBRAM(AddressSet(0x0, 0xff)))
@@ -34,15 +34,15 @@ class AHBFuzzNative(aFlow: Boolean)(implicit p: Parameters) extends LazyModule
   }
 }
 
-class AHBNativeTest(aFlow: Boolean, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  val dut = Module(LazyModule(new AHBFuzzNative(aFlow)).module)
+class AHBNativeTest(aFlow: Boolean, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
+  val dut = Module(LazyModule(new AHBFuzzNative(aFlow, txns)).module)
   io.finished := dut.io.finished
 }
 
-class AHBFuzzMaster(aFlow: Boolean)(implicit p: Parameters) extends LazyModule
+class AHBFuzzMaster(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends LazyModule
 {
   val node  = AHBOutputNode()
-  val fuzz  = LazyModule(new TLFuzzer(5000))
+  val fuzz  = LazyModule(new TLFuzzer(txns))
   val model = LazyModule(new TLRAMModel("AHBFuzzMaster"))
 
   model.node := fuzz.node
@@ -83,9 +83,9 @@ class AHBFuzzSlave()(implicit p: Parameters) extends LazyModule
   }
 }
 
-class AHBFuzzBridge(aFlow: Boolean)(implicit p: Parameters) extends LazyModule
+class AHBFuzzBridge(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends LazyModule
 {
-  val master = LazyModule(new AHBFuzzMaster(aFlow))
+  val master = LazyModule(new AHBFuzzMaster(aFlow, txns))
   val slave  = LazyModule(new AHBFuzzSlave)
 
   slave.node := master.node
@@ -95,7 +95,7 @@ class AHBFuzzBridge(aFlow: Boolean)(implicit p: Parameters) extends LazyModule
   }
 }
 
-class AHBBridgeTest(aFlow: Boolean, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  val dut = Module(LazyModule(new AHBFuzzBridge(aFlow)).module)
+class AHBBridgeTest(aFlow: Boolean, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
+  val dut = Module(LazyModule(new AHBFuzzBridge(aFlow, txns)).module)
   io.finished := dut.io.finished
 }
diff --git a/src/main/scala/uncore/apb/Test.scala b/src/main/scala/uncore/apb/Test.scala
index dccdba8a..2f359f42 100644
--- a/src/main/scala/uncore/apb/Test.scala
+++ b/src/main/scala/uncore/apb/Test.scala
@@ -16,9 +16,9 @@ class RRTest1(address: BigInt)(implicit p: Parameters) extends APBRegisterRouter
   new APBRegBundle((), _)    with RRTest1Bundle)(
   new APBRegModule((), _, _) with RRTest1Module)
 
-class APBFuzzBridge(aFlow: Boolean)(implicit p: Parameters) extends LazyModule
+class APBFuzzBridge(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends LazyModule
 {
-  val fuzz  = LazyModule(new TLFuzzer(5000))
+  val fuzz  = LazyModule(new TLFuzzer(txns))
   val model = LazyModule(new TLRAMModel("APBFuzzMaster"))
   var xbar  = LazyModule(new APBFanout)
   val ram   = LazyModule(new APBRAM(AddressSet(0x0, 0xff)))
@@ -39,7 +39,7 @@ class APBFuzzBridge(aFlow: Boolean)(implicit p: Parameters) extends LazyModule
   }
 }
 
-class APBBridgeTest(aFlow: Boolean, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  val dut = Module(LazyModule(new APBFuzzBridge(aFlow)).module)
+class APBBridgeTest(aFlow: Boolean, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
+  val dut = Module(LazyModule(new APBFuzzBridge(aFlow, txns)).module)
   io.finished := dut.io.finished
 }
diff --git a/src/main/scala/uncore/axi4/Test.scala b/src/main/scala/uncore/axi4/Test.scala
index dcc68b0a..401036ff 100644
--- a/src/main/scala/uncore/axi4/Test.scala
+++ b/src/main/scala/uncore/axi4/Test.scala
@@ -16,9 +16,9 @@ class RRTest1(address: BigInt)(implicit p: Parameters) extends AXI4RegisterRoute
   new AXI4RegBundle((), _)    with RRTest1Bundle)(
   new AXI4RegModule((), _, _) with RRTest1Module)
 
-class AXI4LiteFuzzRAM()(implicit p: Parameters) extends LazyModule
+class AXI4LiteFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyModule
 {
-  val fuzz  = LazyModule(new TLFuzzer(5000))
+  val fuzz  = LazyModule(new TLFuzzer(txns))
   val model = LazyModule(new TLRAMModel("AXI4LiteFuzzRAM"))
   val xbar  = LazyModule(new TLXbar)
   val gpio  = LazyModule(new RRTest1(0x400))
@@ -34,14 +34,14 @@ class AXI4LiteFuzzRAM()(implicit p: Parameters) extends LazyModule
   }
 }
 
-class AXI4LiteFuzzRAMTest(timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  val dut = Module(LazyModule(new AXI4LiteFuzzRAM).module)
+class AXI4LiteFuzzRAMTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
+  val dut = Module(LazyModule(new AXI4LiteFuzzRAM(txns)).module)
   io.finished := dut.io.finished
 }
 
-class AXI4FullFuzzRAM()(implicit p: Parameters) extends LazyModule
+class AXI4FullFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyModule
 {
-  val fuzz  = LazyModule(new TLFuzzer(5000))
+  val fuzz  = LazyModule(new TLFuzzer(txns))
   val model = LazyModule(new TLRAMModel("AXI4FullFuzzRAM"))
   val xbar  = LazyModule(new TLXbar)
   val gpio  = LazyModule(new RRTest0(0x400))
@@ -57,8 +57,8 @@ class AXI4FullFuzzRAM()(implicit p: Parameters) extends LazyModule
   }
 }
 
-class AXI4FullFuzzRAMTest(timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  val dut = Module(LazyModule(new AXI4FullFuzzRAM).module)
+class AXI4FullFuzzRAMTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
+  val dut = Module(LazyModule(new AXI4FullFuzzRAM(txns)).module)
   io.finished := dut.io.finished
 }
 
@@ -66,10 +66,10 @@ trait HasFuzzTarget {
   val fuzzAddr = AddressSet(0x0, 0xfff)
 }
 
-class AXI4FuzzMaster()(implicit p: Parameters) extends LazyModule with HasFuzzTarget
+class AXI4FuzzMaster(txns: Int)(implicit p: Parameters) extends LazyModule with HasFuzzTarget
 {
   val node  = AXI4OutputNode()
-  val fuzz  = LazyModule(new TLFuzzer(5000, overrideAddress = Some(fuzzAddr)))
+  val fuzz  = LazyModule(new TLFuzzer(txns, overrideAddress = Some(fuzzAddr)))
   val model = LazyModule(new TLRAMModel("AXI4FuzzMaster"))
 
   model.node := fuzz.node
@@ -120,9 +120,9 @@ class AXI4FuzzSlave()(implicit p: Parameters) extends LazyModule with HasFuzzTar
   }
 }
 
-class AXI4FuzzBridge()(implicit p: Parameters) extends LazyModule
+class AXI4FuzzBridge(txns: Int)(implicit p: Parameters) extends LazyModule
 {
-  val master = LazyModule(new AXI4FuzzMaster)
+  val master = LazyModule(new AXI4FuzzMaster(txns))
   val slave  = LazyModule(new AXI4FuzzSlave)
 
   slave.node := master.node
@@ -132,7 +132,7 @@ class AXI4FuzzBridge()(implicit p: Parameters) extends LazyModule
   }
 }
 
-class AXI4BridgeTest(timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  val dut = Module(LazyModule(new AXI4FuzzBridge).module)
+class AXI4BridgeTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
+  val dut = Module(LazyModule(new AXI4FuzzBridge(txns)).module)
   io.finished := dut.io.finished
 }
diff --git a/src/main/scala/uncore/tilelink2/Arbiter.scala b/src/main/scala/uncore/tilelink2/Arbiter.scala
index 54e985ac..0c020937 100644
--- a/src/main/scala/uncore/tilelink2/Arbiter.scala
+++ b/src/main/scala/uncore/tilelink2/Arbiter.scala
@@ -94,7 +94,7 @@ object TLArbiter
 /** Synthesizeable unit tests */
 import unittest._
 
-class TestRobin(timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
+class TestRobin(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   val sources = Wire(Vec(6, DecoupledIO(UInt(width=3))))
   val sink = Wire(DecoupledIO(UInt(width=3)))
   val count = RegInit(UInt(0, width=8))
@@ -117,5 +117,5 @@ class TestRobin(timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(
   when (!sink.fire()) { printf("TestRobin: idle (%d %d)\n", valid, ready) }
 
   count := count + UInt(1)
-  io.finished := count >= UInt(128)
+  io.finished := count >= UInt(txns)
 }
diff --git a/src/main/scala/uncore/tilelink2/AsyncCrossing.scala b/src/main/scala/uncore/tilelink2/AsyncCrossing.scala
index 58308822..1159595b 100644
--- a/src/main/scala/uncore/tilelink2/AsyncCrossing.scala
+++ b/src/main/scala/uncore/tilelink2/AsyncCrossing.scala
@@ -137,10 +137,10 @@ class TLAsyncCrossing(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) ext
 /** Synthesizeable unit tests */
 import unittest._
 
-class TLRAMAsyncCrossing(implicit p: Parameters) extends LazyModule {
+class TLRAMAsyncCrossing(txns: Int)(implicit p: Parameters) extends LazyModule {
   val model = LazyModule(new TLRAMModel("AsyncCrossing"))
   val ram  = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
-  val fuzz = LazyModule(new TLFuzzer(5000))
+  val fuzz = LazyModule(new TLFuzzer(txns))
   val cross = LazyModule(new TLAsyncCrossing)
 
   model.node := fuzz.node
@@ -168,6 +168,6 @@ class TLRAMAsyncCrossing(implicit p: Parameters) extends LazyModule {
   }
 }
 
-class TLRAMAsyncCrossingTest(timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMAsyncCrossing).module).io.finished
+class TLRAMAsyncCrossingTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
+  io.finished := Module(LazyModule(new TLRAMAsyncCrossing(txns)).module).io.finished
 }
diff --git a/src/main/scala/uncore/tilelink2/AtomicAutomata.scala b/src/main/scala/uncore/tilelink2/AtomicAutomata.scala
index 79730abc..4c4dbd78 100644
--- a/src/main/scala/uncore/tilelink2/AtomicAutomata.scala
+++ b/src/main/scala/uncore/tilelink2/AtomicAutomata.scala
@@ -293,8 +293,8 @@ import unittest._
 
 //TODO ensure handler will pass through operations to clients that can handle them themselves
 
-class TLRAMAtomicAutomata()(implicit p: Parameters) extends LazyModule {
-  val fuzz = LazyModule(new TLFuzzer(5000))
+class TLRAMAtomicAutomata(txns: Int)(implicit p: Parameters) extends LazyModule {
+  val fuzz = LazyModule(new TLFuzzer(txns))
   val model = LazyModule(new TLRAMModel("AtomicAutomata"))
   val ram  = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
 
@@ -306,6 +306,6 @@ class TLRAMAtomicAutomata()(implicit p: Parameters) extends LazyModule {
   }
 }
 
-class TLRAMAtomicAutomataTest(timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMAtomicAutomata).module).io.finished
+class TLRAMAtomicAutomataTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
+  io.finished := Module(LazyModule(new TLRAMAtomicAutomata(txns)).module).io.finished
 }
diff --git a/src/main/scala/uncore/tilelink2/Fragmenter.scala b/src/main/scala/uncore/tilelink2/Fragmenter.scala
index bd8dd7e7..8110881a 100644
--- a/src/main/scala/uncore/tilelink2/Fragmenter.scala
+++ b/src/main/scala/uncore/tilelink2/Fragmenter.scala
@@ -286,8 +286,8 @@ object TLFragmenter
 /** Synthesizeable unit tests */
 import unittest._
 
-class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int)(implicit p: Parameters) extends LazyModule {
-  val fuzz = LazyModule(new TLFuzzer(5000))
+class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
+  val fuzz = LazyModule(new TLFuzzer(txns))
   val model = LazyModule(new TLRAMModel("Fragmenter"))
   val ram  = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
 
@@ -309,6 +309,6 @@ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int)(implicit p: Parameters) e
   }
 }
 
-class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize)).module).io.finished
+class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
+  io.finished := Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module).io.finished
 }
diff --git a/src/main/scala/uncore/tilelink2/Fuzzer.scala b/src/main/scala/uncore/tilelink2/Fuzzer.scala
index 4eb2288b..5c1e23d6 100644
--- a/src/main/scala/uncore/tilelink2/Fuzzer.scala
+++ b/src/main/scala/uncore/tilelink2/Fuzzer.scala
@@ -211,7 +211,7 @@ class TLFuzzer(
 /** Synthesizeable integration test */
 import unittest._
 
-class TLFuzzRAM()(implicit p: Parameters) extends LazyModule
+class TLFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyModule
 {
   val model = LazyModule(new TLRAMModel("TLFuzzRAM"))
   val ram  = LazyModule(new TLRAM(AddressSet(0x800, 0x7ff)))
@@ -219,7 +219,7 @@ class TLFuzzRAM()(implicit p: Parameters) extends LazyModule
   val gpio = LazyModule(new RRTest1(0x400))
   val xbar = LazyModule(new TLXbar)
   val xbar2= LazyModule(new TLXbar)
-  val fuzz = LazyModule(new TLFuzzer(5000))
+  val fuzz = LazyModule(new TLFuzzer(txns))
   val cross = LazyModule(new TLAsyncCrossing)
 
   model.node := fuzz.node
@@ -251,7 +251,7 @@ class TLFuzzRAM()(implicit p: Parameters) extends LazyModule
   }
 }
 
-class TLFuzzRAMTest(timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  val dut = Module(LazyModule(new TLFuzzRAM).module)
+class TLFuzzRAMTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
+  val dut = Module(LazyModule(new TLFuzzRAM(txns)).module)
   io.finished := dut.io.finished
 }
diff --git a/src/main/scala/uncore/tilelink2/HintHandler.scala b/src/main/scala/uncore/tilelink2/HintHandler.scala
index e52bfaaf..fe13bbb3 100644
--- a/src/main/scala/uncore/tilelink2/HintHandler.scala
+++ b/src/main/scala/uncore/tilelink2/HintHandler.scala
@@ -110,8 +110,8 @@ import unittest._
 
 //TODO ensure handler will pass through hints to clients that can handle them themselves
 
-class TLRAMHintHandler()(implicit p: Parameters) extends LazyModule {
-  val fuzz = LazyModule(new TLFuzzer(5000))
+class TLRAMHintHandler(txns: Int)(implicit p: Parameters) extends LazyModule {
+  val fuzz = LazyModule(new TLFuzzer(txns))
   val model = LazyModule(new TLRAMModel("HintHandler"))
   val ram  = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
 
@@ -123,6 +123,6 @@ class TLRAMHintHandler()(implicit p: Parameters) extends LazyModule {
   }
 }
 
-class TLRAMHintHandlerTest(timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMHintHandler).module).io.finished
+class TLRAMHintHandlerTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
+  io.finished := Module(LazyModule(new TLRAMHintHandler(txns)).module).io.finished
 }
diff --git a/src/main/scala/uncore/tilelink2/Nodes.scala b/src/main/scala/uncore/tilelink2/Nodes.scala
index 51c4626f..8ce68deb 100644
--- a/src/main/scala/uncore/tilelink2/Nodes.scala
+++ b/src/main/scala/uncore/tilelink2/Nodes.scala
@@ -106,7 +106,7 @@ case class TLInternalInputNode(portParams: Seq[TLClientPortParameters]) extends
 /** Synthesizeable unit tests */
 import unittest._
 
-class TLInputNodeTest(timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
+class TLInputNodeTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   class Acceptor extends LazyModule {
     val node = TLInputNode()
     val tlram = LazyModule(new TLRAM(AddressSet(0x54321000, 0xfff)))
@@ -119,7 +119,7 @@ class TLInputNodeTest(timeout: Int = 500000)(implicit p: Parameters) extends Uni
     }
   }
 
-  val fuzzer = LazyModule(new TLFuzzer(5000))
+  val fuzzer = LazyModule(new TLFuzzer(txns))
   LazyModule(new Acceptor).node := TLFragmenter(4, 64)(fuzzer.node)
 
   io.finished := Module(fuzzer.module).io.finished
diff --git a/src/main/scala/uncore/tilelink2/RationalCrossing.scala b/src/main/scala/uncore/tilelink2/RationalCrossing.scala
index 84727ae0..2d42c803 100644
--- a/src/main/scala/uncore/tilelink2/RationalCrossing.scala
+++ b/src/main/scala/uncore/tilelink2/RationalCrossing.scala
@@ -149,9 +149,9 @@ class TLRationalCrossing(direction: RationalDirection = Symmetric)(implicit p: P
 /** Synthesizeable unit tests */
 import unittest._
 
-class TLRAMRationalCrossingSource(name: String)(implicit p: Parameters) extends LazyModule {
+class TLRAMRationalCrossingSource(name: String, txns: Int)(implicit p: Parameters) extends LazyModule {
   val node = TLRationalOutputNode()
-  val fuzz  = LazyModule(new TLFuzzer(5000))
+  val fuzz  = LazyModule(new TLFuzzer(txns))
   val model = LazyModule(new TLRAMModel(name))
 
   model.node := fuzz.node
@@ -179,20 +179,20 @@ class TLRAMRationalCrossingSink(direction: RationalDirection)(implicit p: Parame
   }
 }
 
-class TLRAMRationalCrossing(implicit p: Parameters) extends LazyModule {
-  val sym_fast_source = LazyModule(new TLRAMRationalCrossingSource("RationalCrossing sym_fast"))
+class TLRAMRationalCrossing(txns: Int)(implicit p: Parameters) extends LazyModule {
+  val sym_fast_source = LazyModule(new TLRAMRationalCrossingSource("RationalCrossing sym_fast", txns))
   val sym_slow_sink   = LazyModule(new TLRAMRationalCrossingSink(Symmetric))
   sym_slow_sink.node := sym_fast_source.node
 
-  val sym_slow_source = LazyModule(new TLRAMRationalCrossingSource("RationalCrossing sym_slow"))
+  val sym_slow_source = LazyModule(new TLRAMRationalCrossingSource("RationalCrossing sym_slow", txns))
   val sym_fast_sink   = LazyModule(new TLRAMRationalCrossingSink(Symmetric))
   sym_fast_sink.node := sym_slow_source.node
 
-  val fix_fast_source = LazyModule(new TLRAMRationalCrossingSource("RationalCrossing fast"))
+  val fix_fast_source = LazyModule(new TLRAMRationalCrossingSource("RationalCrossing fast", txns))
   val fix_slow_sink   = LazyModule(new TLRAMRationalCrossingSink(FastToSlow))
   fix_slow_sink.node := fix_fast_source.node
 
-  val fix_slow_source = LazyModule(new TLRAMRationalCrossingSource("RationalCrossing slow"))
+  val fix_slow_source = LazyModule(new TLRAMRationalCrossingSource("RationalCrossing slow", txns))
   val fix_fast_sink   = LazyModule(new TLRAMRationalCrossingSink(SlowToFast))
   fix_fast_sink.node := fix_slow_source.node
 
@@ -222,6 +222,6 @@ class TLRAMRationalCrossing(implicit p: Parameters) extends LazyModule {
   }
 }
 
-class TLRAMRationalCrossingTest(timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMRationalCrossing).module).io.finished
+class TLRAMRationalCrossingTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
+  io.finished := Module(LazyModule(new TLRAMRationalCrossing(txns)).module).io.finished
 }
diff --git a/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala b/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala
index 74072c24..3dca68f2 100644
--- a/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala
+++ b/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala
@@ -255,8 +255,8 @@ class RRTest1(address: BigInt)(implicit p: Parameters) extends TLRegisterRouter(
   new TLRegBundle((), _)    with RRTest1Bundle)(
   new TLRegModule((), _, _) with RRTest1Module)
 
-class FuzzRRTest0()(implicit p: Parameters) extends LazyModule {
-  val fuzz = LazyModule(new TLFuzzer(5000))
+class FuzzRRTest0(txns: Int)(implicit p: Parameters) extends LazyModule {
+  val fuzz = LazyModule(new TLFuzzer(txns))
   val rrtr = LazyModule(new RRTest0(0x400))
 
   rrtr.node := TLFragmenter(4, 32)(TLDelayer(0.1)(fuzz.node))
@@ -266,12 +266,12 @@ class FuzzRRTest0()(implicit p: Parameters) extends LazyModule {
   }
 }
 
-class TLRR0Test(timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new FuzzRRTest0).module).io.finished
+class TLRR0Test(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
+  io.finished := Module(LazyModule(new FuzzRRTest0(txns)).module).io.finished
 }
 
-class FuzzRRTest1()(implicit p: Parameters) extends LazyModule {
-  val fuzz = LazyModule(new TLFuzzer(5000))
+class FuzzRRTest1(txns: Int)(implicit p: Parameters) extends LazyModule {
+  val fuzz = LazyModule(new TLFuzzer(txns))
   val rrtr = LazyModule(new RRTest1(0x400))
 
   rrtr.node := TLFragmenter(4, 32)(TLDelayer(0.1)(fuzz.node))
@@ -281,7 +281,7 @@ class FuzzRRTest1()(implicit p: Parameters) extends LazyModule {
   }
 }
 
-class TLRR1Test(timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new FuzzRRTest1).module).io.finished
+class TLRR1Test(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
+  io.finished := Module(LazyModule(new FuzzRRTest1(txns)).module).io.finished
 }
 
diff --git a/src/main/scala/uncore/tilelink2/SRAM.scala b/src/main/scala/uncore/tilelink2/SRAM.scala
index b0fe86f5..e4b3e43b 100644
--- a/src/main/scala/uncore/tilelink2/SRAM.scala
+++ b/src/main/scala/uncore/tilelink2/SRAM.scala
@@ -91,8 +91,8 @@ class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)
 /** Synthesizeable unit testing */
 import unittest._
 
-class TLRAMSimple(ramBeatBytes: Int)(implicit p: Parameters) extends LazyModule {
-  val fuzz = LazyModule(new TLFuzzer(5000))
+class TLRAMSimple(ramBeatBytes: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
+  val fuzz = LazyModule(new TLFuzzer(txns))
   val model = LazyModule(new TLRAMModel("SRAMSimple"))
   val ram  = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
 
@@ -104,6 +104,6 @@ class TLRAMSimple(ramBeatBytes: Int)(implicit p: Parameters) extends LazyModule
   }
 }
 
-class TLRAMSimpleTest(ramBeatBytes: Int, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMSimple(ramBeatBytes)).module).io.finished
+class TLRAMSimpleTest(ramBeatBytes: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
+  io.finished := Module(LazyModule(new TLRAMSimple(ramBeatBytes, txns)).module).io.finished
 }
diff --git a/src/main/scala/uncore/tilelink2/TestRAM.scala b/src/main/scala/uncore/tilelink2/TestRAM.scala
index f2951492..c1b28f56 100644
--- a/src/main/scala/uncore/tilelink2/TestRAM.scala
+++ b/src/main/scala/uncore/tilelink2/TestRAM.scala
@@ -65,8 +65,8 @@ class TLTestRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int
 /** Synthesizeable unit testing */
 import unittest._
 
-class TLRAMZeroDelay(ramBeatBytes: Int)(implicit p: Parameters) extends LazyModule {
-  val fuzz = LazyModule(new TLFuzzer(5000))
+class TLRAMZeroDelay(ramBeatBytes: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
+  val fuzz = LazyModule(new TLFuzzer(txns))
   val model = LazyModule(new TLRAMModel("ZeroDelay"))
   val ram  = LazyModule(new TLTestRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
 
@@ -78,6 +78,6 @@ class TLRAMZeroDelay(ramBeatBytes: Int)(implicit p: Parameters) extends LazyModu
   }
 }
 
-class TLRAMZeroDelayTest(ramBeatBytes: Int, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMZeroDelay(ramBeatBytes)).module).io.finished
+class TLRAMZeroDelayTest(ramBeatBytes: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
+  io.finished := Module(LazyModule(new TLRAMZeroDelay(ramBeatBytes, txns)).module).io.finished
 }
diff --git a/src/main/scala/uncore/tilelink2/WidthWidget.scala b/src/main/scala/uncore/tilelink2/WidthWidget.scala
index 6aea2fb6..8e27b822 100644
--- a/src/main/scala/uncore/tilelink2/WidthWidget.scala
+++ b/src/main/scala/uncore/tilelink2/WidthWidget.scala
@@ -180,8 +180,8 @@ object TLWidthWidget
 /** Synthesizeable unit tests */
 import unittest._
 
-class TLRAMWidthWidget(first: Int, second: Int)(implicit p: Parameters) extends LazyModule {
-  val fuzz = LazyModule(new TLFuzzer(5000))
+class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
+  val fuzz = LazyModule(new TLFuzzer(txns))
   val model = LazyModule(new TLRAMModel("WidthWidget"))
   val ram  = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
 
@@ -197,6 +197,6 @@ class TLRAMWidthWidget(first: Int, second: Int)(implicit p: Parameters) extends
   }
 }
 
-class TLRAMWidthWidgetTest(little: Int, big: Int, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMWidthWidget(little,big)).module).io.finished
+class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
+  io.finished := Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module).io.finished
 }
diff --git a/src/main/scala/uncore/tilelink2/Xbar.scala b/src/main/scala/uncore/tilelink2/Xbar.scala
index c4507a8c..f59c6ba5 100644
--- a/src/main/scala/uncore/tilelink2/Xbar.scala
+++ b/src/main/scala/uncore/tilelink2/Xbar.scala
@@ -213,8 +213,8 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.lowestIndexFirst)(implicit p:
 /** Synthesizeable unit tests */
 import unittest._
 
-class TLRAMXbar(nManagers: Int)(implicit p: Parameters) extends LazyModule {
-  val fuzz = LazyModule(new TLFuzzer(5000))
+class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
+  val fuzz = LazyModule(new TLFuzzer(txns))
   val model = LazyModule(new TLRAMModel("Xbar"))
   val xbar = LazyModule(new TLXbar)
 
@@ -230,15 +230,15 @@ class TLRAMXbar(nManagers: Int)(implicit p: Parameters) extends LazyModule {
   }
 }
 
-class TLRAMXbarTest(nManagers: Int, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMXbar(nManagers)).module).io.finished
+class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
+  io.finished := Module(LazyModule(new TLRAMXbar(nManagers,txns)).module).io.finished
 }
 
-class TLMulticlientXbar(nManagers: Int, nClients: Int)(implicit p: Parameters) extends LazyModule {
+class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
   val xbar = LazyModule(new TLXbar)
 
   val fuzzers = (0 until nClients) map { n =>
-    val fuzz = LazyModule(new TLFuzzer(5000))
+    val fuzz = LazyModule(new TLFuzzer(txns))
     xbar.node := TLDelayer(0.1)(fuzz.node)
     fuzz
   }
@@ -253,6 +253,6 @@ class TLMulticlientXbar(nManagers: Int, nClients: Int)(implicit p: Parameters) e
   }
 }
 
-class TLMulticlientXbarTest(nManagers: Int, nClients: Int, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLMulticlientXbar(nManagers, nClients)).module).io.finished
+class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
+  io.finished := Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module).io.finished
 }