riscv/rocket-chip
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Remove start address option from AddrMapEntries

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It appears to never be used, and clutters things.  The new invariant is
that AddrMaps are relative and AddrHashMaps are absolute.
This commit is contained in:
Andrew Waterman 2016-04-27 14:52:05 -07:00
parent d3dee2c6c6
commit c8b1f0801b
3 changed files with 18 additions and 29 deletions
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14
junctions/src/main/scala/addrmap.scala
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@ -59,7 +59,7 @@ class AddrMapProt extends Bundle {
val r = Bool() val r = Bool()
} }
case class AddrMapEntry(name: String, start: Option[BigInt], region: MemRegion) case class AddrMapEntry(name: String, region: MemRegion)
case class AddrHashMapEntry(port: Int, start: BigInt, size: BigInt, prot: Int, cacheable: Boolean) case class AddrHashMapEntry(port: Int, start: BigInt, size: BigInt, prot: Int, cacheable: Boolean)
@ -84,16 +84,12 @@ class AddrHashMap(addrmap: AddrMap, start: BigInt = BigInt(0)) {
var ind = 0 var ind = 0
var base = start var base = start
var pairs = Seq[(String, AddrHashMapEntry)]() var pairs = Seq[(String, AddrHashMapEntry)]()
am.foreach { case AddrMapEntry(name, startOpt, region) => am.foreach {
region match { case AddrMapEntry(name, MemSize(size, prot, cacheable)) =>
case MemSize(size, prot, cacheable) => {
if (!startOpt.isEmpty) base = startOpt.get
pairs = (name, AddrHashMapEntry(ind, base, size, prot, cacheable)) +: pairs pairs = (name, AddrHashMapEntry(ind, base, size, prot, cacheable)) +: pairs
base += size base += size
ind += 1 ind += 1
} case AddrMapEntry(name, MemSubmap(size, submap)) =>
case MemSubmap(size, submap) => {
if (!startOpt.isEmpty) base = startOpt.get
val subpairs = genPairs(submap, base).map { val subpairs = genPairs(submap, base).map {
case (subname, AddrHashMapEntry(subind, subbase, subsize, prot, cacheable)) => case (subname, AddrHashMapEntry(subind, subbase, subsize, prot, cacheable)) =>
(name + ":" + subname, (name + ":" + subname,
@ -103,8 +99,6 @@ class AddrHashMap(addrmap: AddrMap, start: BigInt = BigInt(0)) {
ind += subpairs.size ind += subpairs.size
base += size base += size
} }
}
}
pairs pairs
} }

9
junctions/src/main/scala/nasti.scala
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@ -505,21 +505,20 @@ class NastiRecursiveInterconnect(
var lastEnd = base var lastEnd = base
var slaveInd = 0 var slaveInd = 0
val levelSize = addrmap.size val levelSize = addrmap.size
val realAddrMap = new ArraySeq[(BigInt, BigInt)](addrmap.size)
addrmap.zipWithIndex.foreach { case (AddrMapEntry(name, startOpt, region), i) => val realAddrMap = addrmap map { case AddrMapEntry(name, region) =>
val start = startOpt.getOrElse(lastEnd) val start = lastEnd
val size = region.size val size = region.size
require(bigIntPow2(size), require(isPow2(size),
s"Region $name size $size is not a power of 2") s"Region $name size $size is not a power of 2")
require(start % size == 0, require(start % size == 0,
f"Region $name start address 0x$start%x not divisible by 0x$size%x" ) f"Region $name start address 0x$start%x not divisible by 0x$size%x" )
require(start >= lastEnd, require(start >= lastEnd,
f"Region $name start address 0x$start%x before previous region end") f"Region $name start address 0x$start%x before previous region end")
realAddrMap(i) = (start, size)
lastEnd = start + size lastEnd = start + size
(start, size)
} }
val routeSel = (addr: UInt) => { val routeSel = (addr: UInt) => {

4
junctions/src/main/scala/util.scala
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@ -3,10 +3,6 @@ package junctions
import Chisel._ import Chisel._
import cde.Parameters import cde.Parameters
object bigIntPow2 {
def apply(in: BigInt): Boolean = in > 0 && ((in & (in-1)) == 0)
}
class ParameterizedBundle(implicit p: Parameters) extends Bundle { class ParameterizedBundle(implicit p: Parameters) extends Bundle {
override def cloneType = { override def cloneType = {
try { try {