riscv/rocket-chip
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Don't signal access exceptions on invalid PTEs

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The PPN should not be interpreted in this case.
This commit is contained in:
Andrew Waterman 2017-04-04 12:01:59 -07:00 committed by Andrew Waterman
parent 2e09253d26
commit c861c4925e
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocket/PTW.scala
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@ -184,7 +184,7 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
state := s_req state := s_req
count := count + 1 count := count + 1
}.otherwise { }.otherwise {
resp_ae := invalid_paddr resp_ae := pte.v && invalid_paddr
state := s_ready state := s_ready
resp_valid(r_req_dest) := true resp_valid(r_req_dest) := true
} }