riscv/rocket-chip
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Merge remote-tracking branch 'origin/test_mode_reset' into test_mode_reset

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This commit is contained in:
Megan Wachs
2017-09-17 13:51:46 -07:00
parent 215e072e5c 9b75dd7e5b
commit c85333f826
22 changed files with 80 additions and 84 deletions
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2
src/main/scala/devices/debug/DebugTransport.scala
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@ -19,7 +19,7 @@ case class JtagDTMConfig (
// the lines of p(JtagDTMKey).idcodeManufId.U(11.W).
debugIdleCycles : Int)
case object JtagDTMKey extends Field[JtagDTMConfig]
case object JtagDTMKey extends Field[JtagDTMConfig](new JtagDTMKeyDefault())
class JtagDTMKeyDefault extends JtagDTMConfig(
idcodeVersion = 0,

1
src/main/scala/devices/debug/Periphery.scala
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@ -13,6 +13,7 @@ import freechips.rocketchip.util._
/** A knob selecting one of the two possible debug interfaces */
case object IncludeJtagDTM extends Field[Boolean](false)
/** A wrapper bundle containing one of the two possible debug interfaces */
class DebugIO(implicit val p: Parameters) extends ParameterizedBundle()(p) with CanHavePSDTestModeIO {

4
src/main/scala/devices/tilelink/Clint.scala
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@ -30,7 +30,7 @@ case class ClintParams(baseAddress: BigInt = 0x02000000, intStages: Int = 0)
def address = AddressSet(baseAddress, ClintConsts.size-1)
}
case object ClintParams extends Field[ClintParams]
case object ClintKey extends Field(ClintParams())
class CoreplexLocalInterrupter(params: ClintParams)(implicit p: Parameters) extends LazyModule
{
@ -96,6 +96,6 @@ class CoreplexLocalInterrupter(params: ClintParams)(implicit p: Parameters) exte
/** Trait that will connect a Clint to a coreplex */
trait HasPeripheryClint extends HasPeripheryBus {
val clint = LazyModule(new CoreplexLocalInterrupter(p(ClintParams)))
val clint = LazyModule(new CoreplexLocalInterrupter(p(ClintKey)))
clint.node := pbus.toVariableWidthSlaves
}

4
src/main/scala/devices/tilelink/Plic.scala
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@ -58,7 +58,7 @@ case class PLICParams(baseAddress: BigInt = 0xC000000, maxPriorities: Int = 7, i
def address = AddressSet(baseAddress, PLICConsts.size-1)
}
case object PLICParams extends Field[PLICParams]
case object PLICKey extends Field(PLICParams())
/** Platform-Level Interrupt Controller */
class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
@ -238,7 +238,7 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
/** Trait that will connect a PLIC to a coreplex */
trait HasPeripheryPLIC extends HasInterruptBus with HasPeripheryBus {
val plic = LazyModule(new TLPLIC(p(PLICParams)))
val plic = LazyModule(new TLPLIC(p(PLICKey)))
plic.node := pbus.toVariableWidthSlaves
plic.intnode := ibus.toPLIC
}