Instantiate Debug Module (#119)

.gitmodules

@@ -6,7 +6,7 @@
 	url = https://github.com/dramninjasUMD/DRAMSim2.git
 [submodule "riscv-tools"]
 	path = riscv-tools
-	url = https://github.com/ucb-bar/riscv-tools.git
+	url = https://github.com/riscv/riscv-tools.git
 [submodule "rocket"]
 	path = rocket
 	url = https://github.com/ucb-bar/rocket.git

junctions

@@ -1 +1 @@
-Subproject commit b912b7cd1263d7f3b63e6fcb052d9d7493d1b970
+Subproject commit bf5823a6ed211b489359a13697d7db726bcbb123

riscv-tools

@@ -1 +1 @@
-Subproject commit 5e9763fe7306e1214fc6babf05b3f15728932738
+Subproject commit dddbdec89bb045a3cd134f4776619097c838f20a

rocket

@@ -1 +1 @@
-Subproject commit 2519bfde31e07aa2c7b845f523bd01c9b7322441
+Subproject commit ae6ac02c758f14fd594e5707125ae931ea530d75

src/main/scala/Configs.scala

@@ -25,7 +25,7 @@ class BaseConfig extends Config (
     def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
     lazy val internalIOAddrMap: AddrMap = {
       val entries = collection.mutable.ArrayBuffer[AddrMapEntry]()
-      entries += AddrMapEntry("debug", MemSize(1<<12, 1<<12, MemAttr(0)))
+      entries += AddrMapEntry("debug", MemSize(1<<12, 1<<12, MemAttr(AddrMapProt.RWX)))
       entries += AddrMapEntry("bootrom", MemSize(1<<12, 1<<12, MemAttr(AddrMapProt.RX)))
       entries += AddrMapEntry("rtc", MemSize(1<<12, 1<<12, MemAttr(AddrMapProt.RW)))
       for (i <- 0 until site(NTiles))
@@ -205,6 +205,7 @@ class BaseConfig extends Config (
       case RetireWidth => 1
       case UseVM => true
       case UseUser => true
+      case UseDebug => true
       case UsePerfCounters => true
       case FastLoadWord => true
       case FastLoadByte => false
@@ -224,6 +225,7 @@ class BaseConfig extends Config (
       case NExtInterrupts => 2
       case NExtMMIOChannels => 0
       case PLICKey => PLICConfig(site(NTiles), site(UseVM), site(NExtInterrupts), site(NExtInterrupts))
+      case DMKey => new DefaultDebugModuleConfig(site(NTiles), site(XLen))
       case FDivSqrt => true
       case SFMALatency => 2
       case DFMALatency => 3

src/main/scala/RocketChip.scala

@@ -81,6 +81,7 @@ class TopIO(implicit p: Parameters) extends BasicTopIO()(p) {
   val mem = Vec(nMemChannels, new NastiIO)
   val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
   val mmio = Vec(p(NExtMMIOChannels), new NastiIO)
+  val debug = new DebugBusIO()(p).flip
 }
 
 object TopUtils {
@@ -142,6 +143,7 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
   uncore.io.tiles_uncached <> tileList.map(_.io.uncached).flatten
   io.host <> uncore.io.host
   uncore.io.interrupts <> io.interrupts
+  uncore.io.debugBus <> io.debug
 
   io.mmio <> uncore.io.mmio
   io.mem <> uncore.io.mem
@@ -162,6 +164,7 @@ class Uncore(implicit val p: Parameters) extends Module
     val prci = Vec(nTiles, new PRCITileIO).asOutput
     val mmio = Vec(p(NExtMMIOChannels), new NastiIO)
     val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
+    val debugBus = new DebugBusIO()(p).flip
   }
 
   val htif = Module(new Htif(CSRs.mreset)) // One HTIF module per chip
@@ -211,6 +214,11 @@ class Uncore(implicit val p: Parameters) extends Module
       plic.io.devices(i) <> gateway.io.plic
     }
 
+    val debugModule = Module(new DebugModule)
+    val debugModuleAddr = ioAddrHashMap("int:debug")
+    debugModule.io.tl <> mmioNetwork.io.out(debugModuleAddr.port)
+    debugModule.io.db <> io.debugBus
+
     for (i <- 0 until nTiles) {
       val prci = Module(new PRCI)
       val prciAddr = ioAddrHashMap(s"int:prci$i")
@@ -221,7 +229,7 @@ class Uncore(implicit val p: Parameters) extends Module
       prci.io.interrupts.meip := plic.io.harts(plic.cfg.context(i, 'M'))
       if (p(UseVM))
         prci.io.interrupts.seip := plic.io.harts(plic.cfg.context(i, 'S'))
-      prci.io.interrupts.debug := Bool(false)
+      prci.io.interrupts.debug := debugModule.io.debugInterrupts(i)
 
       io.prci(i) := prci.io.tile
       io.prci(i).reset := Reg(next=Reg(next=htif.io.cpu(i).reset)) // TODO
@@ -231,10 +239,6 @@ class Uncore(implicit val p: Parameters) extends Module
     val bootROMAddr = ioAddrHashMap("int:bootrom")
     bootROM.io <> mmioNetwork.io.out(bootROMAddr.port)
 
-    val debugModule = Module(new ROMSlave(Seq())) // TODO
-    val debugModuleAddr = ioAddrHashMap("int:debug")
-    debugModule.io <> mmioNetwork.io.out(debugModuleAddr.port)
-
     val mmioEndpoint = p(NExtMMIOChannels) match {
       case 0 => Module(new NastiErrorSlave).io
       case 1 => io.mmio(0)

src/main/scala/TestBench.scala

@@ -4,6 +4,7 @@ package rocketchip
 
 import Chisel._
 import cde.Parameters
+import uncore.{DbBusConsts, DMKey}
 
 object TestBenchGeneration extends FileSystemUtilities {
   def generateVerilogFragment(
@@ -206,6 +207,22 @@ object TestBenchGeneration extends FileSystemUtilities {
     .io_interrupts_$i (1'b0),
 """ } mkString
 
+    val daw = p(DMKey).nDebugBusAddrSize
+    val dow = DbBusConsts.dbOpSize
+    val ddw = DbBusConsts.dbDataSize
+    val debug_bus = s"""
+  .io_debug_req_ready( ),
+  .io_debug_req_valid(1'b0),
+  .io_debug_req_bits_addr($daw'b0),
+  .io_debug_req_bits_op($dow'b0),
+  .io_debug_req_bits_data($ddw'b0),
+  .io_debug_resp_ready(1'b0),
+  .io_debug_resp_valid( ),
+  .io_debug_resp_bits_resp( ),
+  .io_debug_resp_bits_data( ),
+"""
+
+
     val instantiation = s"""
 `ifdef FPGA
   assign htif_clk = clk;
@@ -220,6 +237,8 @@ object TestBenchGeneration extends FileSystemUtilities {
 
     $interrupts
 
+    $debug_bus
+
 `ifndef FPGA
     .io_host_clk(htif_clk),
     .io_host_clk_edge(),

uncore

@@ -1 +1 @@
-Subproject commit 4fb8f7be64e2c4754f3a97b4f4af09c2e7169f8b
+Subproject commit b04524d2593806e8deed8f253e4e8fe9eac0c495