riscv/rocket-chip
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Instantiate Debug Module (#119)

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This commit is contained in:
Andrew Waterman
2016-06-02 10:53:41 -07:00
parent 1311e78d3f
commit c8338ad809
8 changed files with 36 additions and 11 deletions
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4
src/main/scala/Configs.scala
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@ -25,7 +25,7 @@ class BaseConfig extends Config (
def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
lazy val internalIOAddrMap: AddrMap = {
val entries = collection.mutable.ArrayBuffer[AddrMapEntry]()
entries += AddrMapEntry("debug", MemSize(1<<12, 1<<12, MemAttr(0)))
entries += AddrMapEntry("debug", MemSize(1<<12, 1<<12, MemAttr(AddrMapProt.RWX)))
entries += AddrMapEntry("bootrom", MemSize(1<<12, 1<<12, MemAttr(AddrMapProt.RX)))
entries += AddrMapEntry("rtc", MemSize(1<<12, 1<<12, MemAttr(AddrMapProt.RW)))
for (i <- 0 until site(NTiles))
@ -205,6 +205,7 @@ class BaseConfig extends Config (
case RetireWidth => 1
case UseVM => true
case UseUser => true
case UseDebug => true
case UsePerfCounters => true
case FastLoadWord => true
case FastLoadByte => false
@ -224,6 +225,7 @@ class BaseConfig extends Config (
case NExtInterrupts => 2
case NExtMMIOChannels => 0
case PLICKey => PLICConfig(site(NTiles), site(UseVM), site(NExtInterrupts), site(NExtInterrupts))
case DMKey => new DefaultDebugModuleConfig(site(NTiles), site(XLen))
case FDivSqrt => true
case SFMALatency => 2
case DFMALatency => 3