rocketchip: configString is a lazy property of outer

src/main/scala/rocketchip/Utils.scala

@@ -56,8 +56,8 @@ object GenerateConfigString {
   def apply(p: Parameters, clint: CoreplexLocalInterrupter, plic: TLPLIC, peripheryManagers: Seq[TLManagerParameters]) = {
     val c = CoreplexParameters()(p)
     val res = new StringBuilder
-    res append plic.module.globalConfigString
+    res append plic.globalConfigString
-    res append clint.module.globalConfigString
+    res append clint.globalConfigString
     res append  "core {\n"
     for (i <- 0 until c.nTiles) { // TODO heterogeneous tiles
       val isa = {
@@ -71,8 +71,8 @@ object GenerateConfigString {
       res append s"  $i {\n"
       res append  "    0 {\n"
       res append s"      isa $isa;\n"
-      res append clint.module.hartConfigStrings(i)
+      res append clint.hartConfigStrings(i)
-      res append plic.module.hartConfigStrings(i)
+      res append plic.hartConfigStrings(i)
       res append  "    };\n"
       res append  "  };\n"
     }

src/main/scala/uncore/devices/Plic.scala

@@ -68,6 +68,43 @@ class TLPLIC(supervisor: Boolean, maxPriorities: Int, address: BigInt = 0xC00000
     sourceFn       = { _ => IntSourcePortParameters(Seq(IntSourceParameters(contextsPerHart))) },
     sinkFn         = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) })
 
+  /* Negotiated sizes */
+  def nDevices = intnode.edgesIn.map(_.source.num).sum
+  def nPriorities = min(maxPriorities, nDevices)
+  def nHarts = intnode.edgesOut.map(_.source.num).sum
+
+  def context(i: Int, mode: Char) = mode match {
+    case 'M' => i * contextsPerHart
+    case 'S' => require(supervisor); i * contextsPerHart + 1
+  }
+  def claimAddr(i: Int, mode: Char)  = address + PLICConsts.hartBase(context(i, mode)) + PLICConsts.claimOffset
+  def threshAddr(i: Int, mode: Char) = address + PLICConsts.hartBase(context(i, mode))
+  def enableAddr(i: Int, mode: Char) = address + PLICConsts.enableBase(context(i, mode))
+
+  // Create the global PLIC config string
+  lazy val globalConfigString = Seq(
+    s"plic {\n",
+    s"  priority 0x${address.toString(16)};\n",
+    s"  pending 0x${(address + PLICConsts.pendingBase).toString(16)};\n",
+    s"  ndevs ${nDevices};\n",
+    s"};\n").mkString
+
+  // Create the per-Hart config string
+  lazy val hartConfigStrings = Seq.tabulate(intnode.edgesOut.size) { i => (Seq(
+    s"      plic {\n",
+    s"        m {\n",
+    s"         ie 0x${enableAddr(i, 'M').toString(16)};\n",
+    s"         thresh 0x${threshAddr(i, 'M').toString(16)};\n",
+    s"         claim 0x${claimAddr(i, 'M').toString(16)};\n",
+    s"        };\n") ++ (if (!supervisor) Seq() else Seq(
+    s"        s {\n",
+    s"         ie 0x${enableAddr(i, 'S').toString(16)};\n",
+    s"         thresh 0x${threshAddr(i, 'S').toString(16)};\n",
+    s"         claim 0x${claimAddr(i, 'S').toString(16)};\n",
+    s"        };\n")) ++ Seq(
+    s"      };\n")).mkString
+  }
+
   lazy val module = new LazyModuleImp(this) {
     val io = new Bundle {
       val tl_in = node.bundleIn
@@ -91,45 +128,12 @@ class TLPLIC(supervisor: Boolean, maxPriorities: Int, address: BigInt = 0xC00000
       println(s"  [${s.range.start+1}, ${s.range.end}] => ${s.name}")
     }
 
-    val nDevices = interrupts.size
+    require (nDevices == interrupts.size)
-    val nPriorities = min(maxPriorities, nDevices)
+    require (nHarts == harts.size)
-    val nHarts = harts.size
 
     require(nDevices <= PLICConsts.maxDevices)
     require(nHarts > 0 && nHarts <= PLICConsts.maxHarts)
 
-    def context(i: Int, mode: Char) = mode match {
-      case 'M' => i * contextsPerHart
-      case 'S' => require(supervisor); i * contextsPerHart + 1
-    }
-    def claimAddr(i: Int, mode: Char)  = address + PLICConsts.hartBase(context(i, mode)) + PLICConsts.claimOffset
-    def threshAddr(i: Int, mode: Char) = address + PLICConsts.hartBase(context(i, mode))
-    def enableAddr(i: Int, mode: Char) = address + PLICConsts.enableBase(context(i, mode))
-
-    // Create the global PLIC config string
-    val globalConfigString = Seq(
-      s"plic {\n",
-      s"  priority 0x${address.toString(16)};\n",
-      s"  pending 0x${(address + PLICConsts.pendingBase).toString(16)};\n",
-      s"  ndevs ${nDevices};\n",
-      s"};\n").mkString
-
-    // Create the per-Hart config string
-    val hartConfigStrings = io.harts.zipWithIndex.map { case (_, i) => (Seq(
-      s"      plic {\n",
-      s"        m {\n",
-      s"         ie 0x${enableAddr(i, 'M').toString(16)};\n",
-      s"         thresh 0x${threshAddr(i, 'M').toString(16)};\n",
-      s"         claim 0x${claimAddr(i, 'M').toString(16)};\n",
-      s"        };\n") ++ (if (!supervisor) Seq() else Seq(
-      s"        s {\n",
-      s"         ie 0x${enableAddr(i, 'S').toString(16)};\n",
-      s"         thresh 0x${threshAddr(i, 'S').toString(16)};\n",
-      s"         claim 0x${claimAddr(i, 'S').toString(16)};\n",
-      s"        };\n")) ++ Seq(
-      s"      };\n")).mkString
-    }
-
     // For now, use LevelGateways for all TL2 interrupts
     val gateways = Vec(interrupts.map { case i =>
       val gateway = Module(new LevelGateway)

src/main/scala/uncore/devices/Prci.scala

@@ -63,15 +63,6 @@ trait CoreplexLocalInterrupterModule extends Module with HasRegMap with MixCorep
     tile.mtip := time.asUInt >= timecmp(i).asUInt
   }
 
-  val globalConfigString = Seq(
-    s"rtc {\n",
-    s"  addr 0x${(address.base + ClintConsts.timeOffset).toString(16)};\n",
-    s"};\n").mkString
-  val hartConfigStrings = (0 until p(NTiles)).map { i => Seq(
-    s"      timecmp 0x${(address.base + ClintConsts.timecmpOffset(i)).toString(16)};\n",
-    s"      ipi 0x${(address.base + ClintConsts.msipOffset(i)).toString(16)};\n").mkString
-  }
-
   /* 0000 msip hart 0
    * 0004 msip hart 1
    * 4000 mtimecmp hart 0 lo
@@ -96,3 +87,13 @@ class CoreplexLocalInterrupter(address: BigInt = 0x02000000)(implicit val p: Par
   extends TLRegisterRouter(address, size = ClintConsts.size, beatBytes = p(rocket.XLen)/8, undefZero = false)(
   new TLRegBundle(p, _)    with CoreplexLocalInterrupterBundle)(
   new TLRegModule(p, _, _) with CoreplexLocalInterrupterModule)
+{
+  val globalConfigString = Seq(
+    s"rtc {\n",
+    s"  addr 0x${(address + ClintConsts.timeOffset).toString(16)};\n",
+    s"};\n").mkString
+  val hartConfigStrings = (0 until p(NTiles)).map { i => Seq(
+    s"      timecmp 0x${(address + ClintConsts.timecmpOffset(i)).toString(16)};\n",
+    s"      ipi 0x${(address + ClintConsts.msipOffset(i)).toString(16)};\n").mkString
+  }
+}