rocketchip: configString is a lazy property of outer

src/main/scala/uncore/devices/Prci.scala

@@ -63,15 +63,6 @@ trait CoreplexLocalInterrupterModule extends Module with HasRegMap with MixCorep
     tile.mtip := time.asUInt >= timecmp(i).asUInt
   }
 
-  val globalConfigString = Seq(
-    s"rtc {\n",
-    s"  addr 0x${(address.base + ClintConsts.timeOffset).toString(16)};\n",
-    s"};\n").mkString
-  val hartConfigStrings = (0 until p(NTiles)).map { i => Seq(
-    s"      timecmp 0x${(address.base + ClintConsts.timecmpOffset(i)).toString(16)};\n",
-    s"      ipi 0x${(address.base + ClintConsts.msipOffset(i)).toString(16)};\n").mkString
-  }
-
   /* 0000 msip hart 0
    * 0004 msip hart 1
    * 4000 mtimecmp hart 0 lo
@@ -96,3 +87,13 @@ class CoreplexLocalInterrupter(address: BigInt = 0x02000000)(implicit val p: Par
   extends TLRegisterRouter(address, size = ClintConsts.size, beatBytes = p(rocket.XLen)/8, undefZero = false)(
   new TLRegBundle(p, _)    with CoreplexLocalInterrupterBundle)(
   new TLRegModule(p, _, _) with CoreplexLocalInterrupterModule)
+{
+  val globalConfigString = Seq(
+    s"rtc {\n",
+    s"  addr 0x${(address + ClintConsts.timeOffset).toString(16)};\n",
+    s"};\n").mkString
+  val hartConfigStrings = (0 until p(NTiles)).map { i => Seq(
+    s"      timecmp 0x${(address + ClintConsts.timecmpOffset(i)).toString(16)};\n",
+    s"      ipi 0x${(address + ClintConsts.msipOffset(i)).toString(16)};\n").mkString
+  }
+}