riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

fix mul/div when waddr=0, can't believe torture didn't find this one

Browse Source
This commit is contained in:
Yunsup Lee 2012-03-01 10:14:49 -08:00
parent c6162ac743
commit c7b01230f4
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
rocket/src/main/scala/ctrl.scala
View File

@ -771,9 +771,9 @@ class rocketCtrl extends Component
io.dpath.fn_dw := id_fn_dw.toBool; io.dpath.fn_dw := id_fn_dw.toBool;
io.dpath.fn_alu := id_fn_alu; io.dpath.fn_alu := id_fn_alu;
io.dpath.div_fn := id_div_fn; io.dpath.div_fn := id_div_fn;
io.dpath.div_val := id_div_val.toBool; io.dpath.div_val := id_div_val.toBool && id_waddr != UFix(0);
io.dpath.mul_fn := id_mul_fn; io.dpath.mul_fn := id_mul_fn;
io.dpath.mul_val := id_mul_val.toBool; io.dpath.mul_val := id_mul_val.toBool && id_waddr != UFix(0);
io.dpath.ex_fp_val:= ex_reg_fp_val; io.dpath.ex_fp_val:= ex_reg_fp_val;
io.dpath.mem_fp_val:= mem_reg_fp_val; io.dpath.mem_fp_val:= mem_reg_fp_val;
io.dpath.ex_wen := ex_reg_wen; io.dpath.ex_wen := ex_reg_wen;