Get rid of NASTI memory interconnects
These were made for a previous Hurricane tapeout, but we are now doing all of the memory routing in TileLink, so they are no longer needed.
This commit is contained in:
Howard Mao
parent
7d93fd3bfc
commit
c77c244016
@ -1,109 +0,0 @@
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package junctions
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import Chisel._
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import cde.Parameters
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class NastiDemuxDriver(n: Int)(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val start = Bool(INPUT)
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val finished = Bool(OUTPUT)
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val nasti = new NastiIO
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val select = UInt(OUTPUT, log2Up(n))
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}
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val (s_idle :: s_write_addr :: s_write_data :: s_write_resp ::
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s_read_addr :: s_read_resp :: s_done :: Nil) = Enum(Bits(), 7)
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val state = Reg(init = s_idle)
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val select = Reg(init = UInt(0, log2Up(n)))
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when (state === s_idle && io.start) { state := s_write_addr }
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when (io.nasti.aw.fire()) { state := s_write_data }
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when (io.nasti.w.fire()) { state := s_write_resp }
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when (io.nasti.b.fire()) { state := s_read_addr }
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when (io.nasti.ar.fire()) { state := s_read_resp }
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when (io.nasti.r.fire()) {
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when (select === UInt(n - 1)) {
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state := s_done
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} .otherwise {
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select := select + UInt(1)
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state := s_write_addr
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}
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}
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io.nasti.aw.valid := (state === s_write_addr)
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io.nasti.aw.bits := NastiWriteAddressChannel(
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id = UInt(0),
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addr = UInt(0),
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size = UInt("b011"))
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io.nasti.w.valid := (state === s_write_data)
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io.nasti.w.bits := NastiWriteDataChannel(data = select)
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io.nasti.b.ready := (state === s_write_resp)
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io.nasti.ar.valid := (state === s_read_addr)
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io.nasti.ar.bits := NastiReadAddressChannel(
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id = UInt(0),
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addr = UInt(0),
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size = UInt("b011"))
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io.nasti.r.ready := (state === s_read_resp)
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io.finished := (state === s_done)
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io.select := select
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assert(!io.nasti.r.valid || io.nasti.r.bits.data === select,
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"NASTI DeMux test: Read data did not match")
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}
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class NastiDemuxSlave(implicit p: Parameters) extends NastiModule()(p) {
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val io = (new NastiIO).flip
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val (s_write_wait :: s_write_data :: s_write_resp ::
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s_read_wait :: s_read_resp :: s_done :: Nil) = Enum(Bits(), 6)
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val state = Reg(init = s_write_wait)
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val value = Reg(UInt(width = 64))
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val id = Reg(UInt(width = nastiXIdBits))
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when (io.aw.fire()) {
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id := io.aw.bits.id
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state := s_write_data
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}
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when (io.w.fire()) {
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value := io.w.bits.data
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state := s_write_resp
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}
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when (io.b.fire()) { state := s_read_wait }
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when (io.ar.fire()) {
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id := io.ar.bits.id
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state := s_read_resp
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}
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when (io.r.fire()) { state := s_done }
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io.aw.ready := (state === s_write_wait)
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io.w.ready := (state === s_write_data)
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io.b.valid := (state === s_write_resp)
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io.b.bits := NastiWriteResponseChannel(id = id)
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io.ar.ready := (state === s_read_wait)
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io.r.valid := (state === s_read_resp)
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io.r.bits := NastiReadDataChannel(id = id, data = value)
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}
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class NastiMemoryDemuxTest(implicit p: Parameters) extends unittest.UnitTest {
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val nSlaves = 4
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val driver = Module(new NastiDemuxDriver(nSlaves))
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driver.io.start := io.start
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io.finished := driver.io.finished
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val demux = Module(new NastiMemoryDemux(nSlaves))
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demux.io.master <> driver.io.nasti
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demux.io.select := driver.io.select
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for (i <- 0 until nSlaves) {
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val slave = Module(new NastiDemuxSlave)
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slave.io <> demux.io.slaves(i)
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}
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}
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@ -553,171 +553,6 @@ class NastiRecursiveInterconnect(val nMasters: Int, addrMap: AddrMap)
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}
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}
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class ChannelHelper(nChannels: Int)
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(implicit val p: Parameters) extends HasNastiParameters {
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val dataBytes = p(MIFDataBits) * p(MIFDataBeats) / 8
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val chanSelBits = log2Ceil(nChannels)
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val selOffset = log2Up(dataBytes)
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val blockOffset = selOffset + chanSelBits
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def getSelect(addr: UInt) =
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if (nChannels > 1) addr(blockOffset - 1, selOffset) else UInt(0)
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def getAddr(addr: UInt) =
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if (nChannels > 1)
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Cat(addr(nastiXAddrBits - 1, blockOffset), addr(selOffset - 1, 0))
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else addr
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}
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class NastiMemoryInterconnect(
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nBanksPerChannel: Int, nChannels: Int)
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(implicit p: Parameters) extends NastiInterconnect()(p) {
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val nBanks = nBanksPerChannel * nChannels
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val nMasters = nBanks
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val nSlaves = nChannels
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val chanHelper = new ChannelHelper(nChannels)
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def connectChannel(outer: NastiIO, inner: NastiIO) {
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outer <> inner
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outer.ar.bits.addr := chanHelper.getAddr(inner.ar.bits.addr)
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outer.aw.bits.addr := chanHelper.getAddr(inner.aw.bits.addr)
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}
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for (i <- 0 until nChannels) {
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/* Bank assignments to channels are strided so that consecutive banks
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* map to different channels. That way, consecutive cache lines also
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* map to different channels */
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val banks = (i until nBanks by nChannels).map(j => io.masters(j))
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val channelArb = Module(new NastiArbiter(nBanksPerChannel))
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channelArb.io.master <> banks
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connectChannel(io.slaves(i), channelArb.io.slave)
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}
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}
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/** Allows users to switch between various memory configurations. Note that
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* this is a dangerous operation: not only does switching the select input to
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* this module violate Nasti, it also causes the memory of the machine to
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* become garbled. It's expected that select only changes at boot time, as
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* part of the memory controller configuration. */
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class NastiMemorySelectorIO(val nBanks: Int, val maxMemChannels: Int, nConfigs: Int)
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(implicit p: Parameters)
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extends NastiInterconnectIO(nBanks, maxMemChannels) {
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val select = UInt(INPUT, width = log2Up(nConfigs))
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override def cloneType =
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new NastiMemorySelectorIO(nMasters, nSlaves, nConfigs).asInstanceOf[this.type]
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}
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class NastiMemorySelector(nBanks: Int, maxMemChannels: Int, configs: Seq[Int])
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(implicit p: Parameters)
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extends NastiInterconnect()(p) {
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val nMasters = nBanks
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val nSlaves = maxMemChannels
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val nConfigs = configs.size
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override lazy val io = new NastiMemorySelectorIO(nBanks, maxMemChannels, nConfigs)
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def muxOnSelect(up: DecoupledIO[Bundle], dn: DecoupledIO[Bundle], active: Bool): Unit = {
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when (active) { dn.bits := up.bits }
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when (active) { up.ready := dn.ready }
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when (active) { dn.valid := up.valid }
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}
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def muxOnSelect(up: NastiIO, dn: NastiIO, active: Bool): Unit = {
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muxOnSelect(up.aw, dn.aw, active)
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muxOnSelect(up.w, dn.w, active)
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muxOnSelect(dn.b, up.b, active)
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muxOnSelect(up.ar, dn.ar, active)
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muxOnSelect(dn.r, up.r, active)
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}
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def muxOnSelect(up: Vec[NastiIO], dn: Vec[NastiIO], active: Bool) : Unit = {
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for (i <- 0 until up.size)
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muxOnSelect(up(i), dn(i), active)
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}
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/* Disconnects a vector of Nasti ports, which involves setting them to
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* invalid. Due to Chisel reasons, we need to also set the bits to 0 (since
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* there can't be any unconnected inputs). */
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def disconnectSlave(slave: Vec[NastiIO]) = {
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slave.foreach{ m =>
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m.aw.valid := Bool(false)
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m.aw.bits := m.aw.bits.fromBits( UInt(0) )
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m.w.valid := Bool(false)
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m.w.bits := m.w.bits.fromBits( UInt(0) )
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m.b.ready := Bool(false)
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m.ar.valid := Bool(false)
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m.ar.bits := m.ar.bits.fromBits( UInt(0) )
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m.r.ready := Bool(false)
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}
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}
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def disconnectMaster(master: Vec[NastiIO]) = {
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master.foreach{ m =>
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m.aw.ready := Bool(false)
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m.w.ready := Bool(false)
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m.b.valid := Bool(false)
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m.b.bits := m.b.bits.fromBits( UInt(0) )
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m.ar.ready := Bool(false)
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m.r.valid := Bool(false)
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m.r.bits := m.r.bits.fromBits( UInt(0) )
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}
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}
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/* Provides default wires on all our outputs. */
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disconnectMaster(io.masters)
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disconnectSlave(io.slaves)
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/* Constructs interconnects for each of the layouts suggested by the
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* configuration and switches between them based on the select input. */
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configs.zipWithIndex.foreach{ case (nChannels, select) =>
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val nBanksPerChannel = nBanks / nChannels
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val ic = Module(new NastiMemoryInterconnect(nBanksPerChannel, nChannels))
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disconnectMaster(ic.io.slaves)
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disconnectSlave(ic.io.masters)
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muxOnSelect( io.masters, ic.io.masters, io.select === UInt(select))
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muxOnSelect(ic.io.slaves, io.slaves, io.select === UInt(select))
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}
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}
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class NastiMemoryDemux(nRoutes: Int)(implicit p: Parameters) extends NastiModule()(p) {
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val io = new Bundle {
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val master = (new NastiIO).flip
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val slaves = Vec(nRoutes, new NastiIO)
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val select = UInt(INPUT, log2Up(nRoutes))
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}
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def connectReqChannel[T <: Data](idx: Int, out: DecoupledIO[T], in: DecoupledIO[T]) {
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out.valid := in.valid && io.select === UInt(idx)
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out.bits := in.bits
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when (io.select === UInt(idx)) { in.ready := out.ready }
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}
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def connectRespChannel[T <: Data](idx: Int, out: DecoupledIO[T], in: DecoupledIO[T]) {
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when (io.select === UInt(idx)) { out.valid := in.valid }
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when (io.select === UInt(idx)) { out.bits := in.bits }
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in.ready := out.ready && io.select === UInt(idx)
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}
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io.master.ar.ready := Bool(false)
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io.master.aw.ready := Bool(false)
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io.master.w.ready := Bool(false)
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io.master.r.valid := Bool(false)
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io.master.r.bits := NastiReadDataChannel(id = UInt(0), data = UInt(0))
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io.master.b.valid := Bool(false)
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io.master.b.bits := NastiWriteResponseChannel(id = UInt(0))
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io.slaves.zipWithIndex.foreach { case (slave, i) =>
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connectReqChannel(i, slave.ar, io.master.ar)
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connectReqChannel(i, slave.aw, io.master.aw)
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connectReqChannel(i, slave.w, io.master.w)
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connectRespChannel(i, io.master.r, slave.r)
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connectRespChannel(i, io.master.b, slave.b)
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}
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}
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object AsyncNastiCrossing {
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// takes from_source from the 'from' clock domain to the 'to' clock domain
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def apply(from_clock: Clock, from_reset: Bool, from_source: NastiIO, to_clock: Clock, to_reset: Bool, depth: Int = 8, sync: Int = 3) = {
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@ -12,7 +12,6 @@ class WithJunctionsUnitTests extends Config(
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case rocket.XLen => 64
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case UnitTests => (p: Parameters) => Seq(
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Module(new junctions.MultiWidthFifoTest),
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Module(new junctions.NastiMemoryDemuxTest()(p)),
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Module(new junctions.HastiTest()(p)))
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case _ => throw new CDEMatchError
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})
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