diff --git a/chisel3 b/chisel3
index 2e9b41ca..3eb51f84 160000
--- a/chisel3
+++ b/chisel3
@@ -1 +1 @@
-Subproject commit 2e9b41cafe9158f20ecb03ae9eabecb82e557829
+Subproject commit 3eb51f8484ad21d8a39da1ab7b036f1bb3bbe102
diff --git a/firrtl b/firrtl
index 85dc973e..6f4c0e8b 160000
--- a/firrtl
+++ b/firrtl
@@ -1 +1 @@
-Subproject commit 85dc973ecc3042370f218b77dfa0990fde6c2e0f
+Subproject commit 6f4c0e8b56db79e378965420d4799fca249f9bbe
diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index ffbea713..3d29fb8b 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -27,7 +27,6 @@ class BaseConfig extends Config (
       val entries = collection.mutable.ArrayBuffer[AddrMapEntry]()
       entries += AddrMapEntry("debug", MemSize(4096, MemAttr(AddrMapProt.RWX)))
       entries += AddrMapEntry("bootrom", MemSize(4096, MemAttr(AddrMapProt.RX)))
-      entries += AddrMapEntry("rtc", MemSize(4096, MemAttr(AddrMapProt.RW)))
       entries += AddrMapEntry("plic", MemRange(0x40000000, 0x4000000, MemAttr(AddrMapProt.RW)))
       entries += AddrMapEntry("prci", MemSize(0x4000000, MemAttr(AddrMapProt.RW)))
       new AddrMap(entries)
@@ -57,17 +56,13 @@ class BaseConfig extends Config (
       val plicInfo = site(PLICKey)
       val xLen = site(XLen)
       val res = new StringBuilder
-      res append  "platform {\n"
-      res append  "  vendor ucb;\n"
-      res append  "  arch rocket;\n"
-      res append  "};\n"
       res append  "plic {\n"
       res append s"  priority 0x${plicAddr.toString(16)};\n"
       res append s"  pending 0x${(plicAddr + plicInfo.pendingBase).toString(16)};\n"
       res append s"  ndevs ${plicInfo.nDevices};\n"
       res append  "};\n"
       res append  "rtc {\n"
-      res append s"  addr 0x${addrMap("io:int:rtc").start.toString(16)};\n"
+      res append s"  addr 0x${(prciAddr + PRCI.time).toString(16)};\n"
       res append  "};\n"
       res append  "ram {\n"
       res append  "  0 {\n"
@@ -78,12 +73,11 @@ class BaseConfig extends Config (
       res append  "core {\n"
       for (i <- 0 until site(NTiles)) {
         val isa = s"rv${site(XLen)}im${if (site(UseAtomics)) "a" else ""}${if (site(UseFPU)) "fd" else ""}"
-        val timecmpAddr = addrMap("io:int:rtc").start + 8*(i+1)
         res append s"  $i {\n"
         res append  "    0 {\n"
         res append s"      isa $isa;\n"
-        res append s"      timecmp 0x${timecmpAddr.toString(16)};\n"
-        res append s"      ipi 0x${(prciAddr + 4*i).toString(16)};\n"
+        res append s"      timecmp 0x${(prciAddr + PRCI.timecmp(i)).toString(16)};\n"
+        res append s"      ipi 0x${(prciAddr + PRCI.msip(i)).toString(16)};\n"
         res append s"      plic {\n"
         res append s"        m {\n"
         res append s"         ie 0x${(plicAddr + plicInfo.enableAddr(i, 'M')).toString(16)};\n"
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index ab6f7c0d..a02f891e 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -41,6 +41,8 @@ case object ConfigString extends Field[Array[Byte]]
 case object NExtInterrupts extends Field[Int]
 /** Interrupt controller configuration */
 case object PLICKey extends Field[PLICConfig]
+/** Number of clock cycles per RTC tick */
+case object RTCPeriod extends Field[Int]
 
 case object UseStreamLoopback extends Field[Boolean]
 case object StreamLoopbackSize extends Field[Int]
@@ -204,9 +206,6 @@ class Uncore(implicit val p: Parameters) extends Module
     val mmioNetwork = Module(new TileLinkRecursiveInterconnect(1, ioAddrMap))
     TileLinkWidthAdapter(outmemsys.io.mmio, mmioNetwork.io.in.head)
 
-    val rtc = Module(new RTC(p(NTiles)))
-    rtc.io.tl <> mmioNetwork.port("int:rtc")
-
     val plic = Module(new PLIC(p(PLICKey)))
     plic.io.tl <> mmioNetwork.port("int:plic")
     for (i <- 0 until io.interrupts.size) {
@@ -222,9 +221,9 @@ class Uncore(implicit val p: Parameters) extends Module
     val prci = Module(new PRCI)
     prci.io.tl <> mmioNetwork.port("int:prci")
     io.prci := prci.io.tiles
+    prci.io.rtcTick := Counter(p(RTCPeriod)).inc() // placeholder for real RTC
 
     for (i <- 0 until nTiles) {
-      prci.io.interrupts(i).mtip := rtc.io.irqs(i)
       prci.io.interrupts(i).meip := plic.io.harts(plic.cfg.context(i, 'M'))
       if (p(UseVM))
         prci.io.interrupts(i).seip := plic.io.harts(plic.cfg.context(i, 'S'))
diff --git a/uncore b/uncore
index 689a3373..99f0c8dc 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit 689a3373de64fd3dd6904a6b0f7a2d0d642d6f8d
+Subproject commit 99f0c8dcae783d19ed5d1192b4d658bcc2b65e5a