From c70045b8b3020f58fff0e2c3b3869a1e9917d6f7 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Sat, 17 Sep 2016 00:16:40 -0700
Subject: [PATCH] Utils: express cacheability from TL2 to TL1

---
 src/main/scala/rocketchip/Utils.scala | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/main/scala/rocketchip/Utils.scala b/src/main/scala/rocketchip/Utils.scala
index 8f27cc1b..4ece9f38 100644
--- a/src/main/scala/rocketchip/Utils.scala
+++ b/src/main/scala/rocketchip/Utils.scala
@@ -66,10 +66,16 @@ object GenerateGlobalAddrMap {
     }
 
     lazy val tl2Devices = peripheryManagers.map { manager =>
+      val cacheable = manager.regionType match {
+        case RegionType.CACHED   => true
+        case RegionType.TRACKED  => true
+        case RegionType.UNCACHED => true
+        case _ => false
+      }
       val attr = MemAttr(
         (if (manager.supportsGet)     AddrMapProt.R else 0) |
         (if (manager.supportsPutFull) AddrMapProt.W else 0) |
-        (if (manager.executable)      AddrMapProt.X else 0))
+        (if (manager.executable)      AddrMapProt.X else 0), cacheable)
       val multi = manager.address.size > 1
       manager.address.zipWithIndex.map { case (address, i) =>
         require (!address.strided) // TL1 can't do this