From aa22f175c3844598023015e1d94935b8dbabcb23 Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Mon, 14 Mar 2016 14:12:21 -0700 Subject: [PATCH 1/2] Add cloneType methods for Chisel3 --- uncore/src/main/scala/htif.scala | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/uncore/src/main/scala/htif.scala b/uncore/src/main/scala/htif.scala index 1391d71c..42f6547d 100644 --- a/uncore/src/main/scala/htif.scala +++ b/uncore/src/main/scala/htif.scala @@ -38,6 +38,8 @@ class HostIO(w: Int) extends Bundle { val in = Decoupled(Bits(width = w)).flip val out = Decoupled(Bits(width = w)) val debug_stats_csr = Bool(OUTPUT) + + override def cloneType = new HostIO(w).asInstanceOf[this.type] } class HtifIO(implicit p: Parameters) extends HtifBundle()(p) { @@ -235,6 +237,8 @@ class NastiIOHostIOConverter(htifW: Int)(implicit val p: Parameters) val reset = Bool(OUTPUT) } + def cloneType = new NastiIOHostIOConverter(htifW).asInstanceOf[this.type] + val raddr = io.nasti.ar.bits.addr(6, 2) val waddr = io.nasti.aw.bits.addr(6, 2) From c9e1b729725f6f10abff66ddb017897119b397d0 Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Mon, 14 Mar 2016 16:53:55 -0700 Subject: [PATCH 2/2] Don't assign SInt(-1) to a UInt --- uncore/src/main/scala/cache.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/uncore/src/main/scala/cache.scala b/uncore/src/main/scala/cache.scala index d03ef445..6d7c1241 100644 --- a/uncore/src/main/scala/cache.scala +++ b/uncore/src/main/scala/cache.scala @@ -953,7 +953,7 @@ class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTra io.data.write.bits.way_en := xact_way_en io.data.write.bits.addr_idx := xact_addr_idx io.data.write.bits.addr_beat := curr_write_beat - io.data.write.bits.wmask := SInt(-1) // Always writes a full beat + io.data.write.bits.wmask := ~UInt(0, io.data.write.bits.wmask.getWidth) io.data.write.bits.data := data_buffer(curr_write_beat) // soon as the data is released, granted, put, or read from the cache