riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Chisel3: Don't use Vec.fill for IOs

Browse Source
This commit is contained in:
Andrew Waterman
2015-09-20 13:43:39 -07:00
parent fd58c52250
commit c6bcc832a1
2 changed files with 11 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/Network.scala
View File

@@ -33,8 +33,8 @@ abstract class RocketChipNetwork(
val nClients = params(TLNClients) val nClients = params(TLNClients)
val nManagers = params(TLNManagers) val nManagers = params(TLNManagers)
val io = new Bundle { val io = new Bundle {
val clients = Vec.fill(nClients){new ClientTileLinkIO}.flip val clients = Vec(new ClientTileLinkIO, nClients).flip
val managers = Vec.fill(nManagers){new ManagerTileLinkIO}.flip val managers = Vec(new ManagerTileLinkIO, nManagers).flip
} }
val clients = io.clients.zipWithIndex.map { val clients = io.clients.zipWithIndex.map {

18
src/main/scala/RocketChip.scala
View File

@@ -61,7 +61,7 @@ class TopIO extends BasicTopIO {
} }
class MultiChannelTopIO extends BasicTopIO with TopLevelParameters { class MultiChannelTopIO extends BasicTopIO with TopLevelParameters {
val mem = Vec.fill(nMemChannels){ new MemIO } val mem = Vec(new MemIO, nMemChannels)
} }
/** Top-level module for the chip */ /** Top-level module for the chip */
@@ -116,10 +116,10 @@ class MultiChannelTop extends Module with TopLevelParameters {
class Uncore extends Module with TopLevelParameters { class Uncore extends Module with TopLevelParameters {
val io = new Bundle { val io = new Bundle {
val host = new HostIO val host = new HostIO
val mem = Vec.fill(nMemChannels){ new MemIO } val mem = Vec(new MemIO, nMemChannels)
val tiles_cached = Vec.fill(nTiles){new ClientTileLinkIO}.flip val tiles_cached = Vec(new ClientTileLinkIO, nTiles).flip
val tiles_uncached = Vec.fill(nTiles){new ClientUncachedTileLinkIO}.flip val tiles_uncached = Vec(new ClientUncachedTileLinkIO, nTiles).flip
val htif = Vec.fill(nTiles){new HTIFIO}.flip val htif = Vec(new HTIFIO, nTiles).flip
val mem_backup_ctrl = new MemBackupCtrlIO val mem_backup_ctrl = new MemBackupCtrlIO
} }
@@ -148,11 +148,11 @@ class Uncore extends Module with TopLevelParameters {
*/ */
class OuterMemorySystem extends Module with TopLevelParameters { class OuterMemorySystem extends Module with TopLevelParameters {
val io = new Bundle { val io = new Bundle {
val tiles_cached = Vec.fill(nTiles){new ClientTileLinkIO}.flip val tiles_cached = Vec(new ClientTileLinkIO, nTiles).flip
val tiles_uncached = Vec.fill(nTiles){new ClientUncachedTileLinkIO}.flip val tiles_uncached = Vec(new ClientUncachedTileLinkIO, nTiles).flip
val htif_uncached = (new ClientUncachedTileLinkIO).flip val htif_uncached = (new ClientUncachedTileLinkIO).flip
val incoherent = Vec.fill(nTiles){Bool()}.asInput val incoherent = Vec(Bool(), nTiles).asInput
val mem = Vec.fill(nMemChannels){ new MemIO } val mem = Vec(new MemIO, nMemChannels)
val mem_backup = new MemSerializedIO(htifW) val mem_backup = new MemSerializedIO(htifW)
val mem_backup_en = Bool(INPUT) val mem_backup_en = Bool(INPUT)
} }