don't dequeue probe queue during reset
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0258dfb23f
commit
c6ac836581
@ -140,6 +140,8 @@ class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component {
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val mem_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES)))
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val mem_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES)))
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val mem_cnt_next = mem_cnt + UFix(1)
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val mem_cnt_next = mem_cnt + UFix(1)
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val mem_cnt_max = ~UFix(0, width = log2Up(REFILL_CYCLES))
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val mem_cnt_max = ~UFix(0, width = log2Up(REFILL_CYCLES))
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val p_req_initial_flags = Bits(width = ntiles)
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p_req_initial_flags := ~(io.tile_incoherent | UFixToOH(io.alloc_req.bits.tile_id(log2Up(ntiles)-1,0))) //TODO: Broadcast only
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io.busy := state != s_idle
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io.busy := state != s_idle
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io.addr := addr_
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io.addr := addr_
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@ -178,15 +180,14 @@ class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component {
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tile_xact_id_ := io.alloc_req.bits.xact_init.tile_xact_id
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tile_xact_id_ := io.alloc_req.bits.xact_init.tile_xact_id
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x_init_data_needs_write := co.messageHasData(io.alloc_req.bits.xact_init)
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x_init_data_needs_write := co.messageHasData(io.alloc_req.bits.xact_init)
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x_needs_read := co.needsMemRead(io.alloc_req.bits.xact_init.x_type, UFix(0))
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x_needs_read := co.needsMemRead(io.alloc_req.bits.xact_init.x_type, UFix(0))
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val p_req_initial_flags = ~(io.tile_incoherent | UFixToOH(io.alloc_req.bits.tile_id)) //TODO: Broadcast only
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p_req_flags := p_req_initial_flags
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p_req_flags := p_req_initial_flags(ntiles-1,0)
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mem_cnt := UFix(0)
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mem_cnt := UFix(0)
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p_w_mem_cmd_sent := Bool(false)
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p_w_mem_cmd_sent := Bool(false)
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x_w_mem_cmd_sent := Bool(false)
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x_w_mem_cmd_sent := Bool(false)
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io.pop_x_init := UFix(1) << io.alloc_req.bits.tile_id
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io.pop_x_init := UFix(1) << io.alloc_req.bits.tile_id
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if(ntiles > 1) {
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if(ntiles > 1) {
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p_rep_count := UFix(ntiles-1)
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p_rep_count := PopCount(p_req_initial_flags)
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state := Mux(p_req_initial_flags(ntiles-1,0).orR, s_probe, s_mem)
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state := Mux(p_req_initial_flags.orR, s_probe, s_mem)
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} else state := s_mem
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} else state := s_mem
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}
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}
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}
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}
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