riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

[coreplex] TileId moved to groundtest

Browse Source
This commit is contained in:
Henry Cook 2016-11-22 10:53:44 -08:00
parent 612f96b2af
commit c65c255815
2 changed files with 2 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/main/scala/groundtest/Coreplex.scala
View File

@ -6,9 +6,10 @@ import diplomacy._
import coreplex._ import coreplex._
import uncore.devices.NTiles import uncore.devices.NTiles
import uncore.tilelink2._ import uncore.tilelink2._
import rocket.TileId
import uncore.tilelink.TLId import uncore.tilelink.TLId
case object TileId extends Field[Int]
class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex { class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex {
val tiles = List.tabulate(p(NTiles)) { i => val tiles = List.tabulate(p(NTiles)) { i =>
LazyModule(new GroundTestTile()(p.alterPartial({ LazyModule(new GroundTestTile()(p.alterPartial({

2
src/main/scala/rocket/tile.scala
View File

@ -14,7 +14,6 @@ import config._
import scala.collection.mutable.ListBuffer import scala.collection.mutable.ListBuffer
case object BuildRoCC extends Field[Seq[RoccParameters]] case object BuildRoCC extends Field[Seq[RoccParameters]]
case object TileId extends Field[Int]
case class RoccParameters( case class RoccParameters(
opcodes: OpcodeSet, opcodes: OpcodeSet,
@ -30,7 +29,6 @@ class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
val dcacheParams = coreParams.alterPartial({ val dcacheParams = coreParams.alterPartial({
case CacheName => CacheName("L1D") case CacheName => CacheName("L1D")
case TLId => "L1toL2" case TLId => "L1toL2"
case TileId => tileId // TODO using this messes with Heirarchical P&R: change to io.hartid?
}) })
val icacheParams = coreParams.alterPartial({ val icacheParams = coreParams.alterPartial({
case CacheName => CacheName("L1I") case CacheName => CacheName("L1I")