riscv/rocket-chip
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[coreplex] TileId moved to groundtest

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This commit is contained in:
Henry Cook
2016-11-22 10:53:44 -08:00
parent 612f96b2af
commit c65c255815
2 changed files with 2 additions and 3 deletions
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src/main/scala/rocket/tile.scala
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@ -14,7 +14,6 @@ import config._
import scala.collection.mutable.ListBuffer
case object BuildRoCC extends Field[Seq[RoccParameters]]
case object TileId extends Field[Int]
case class RoccParameters(
opcodes: OpcodeSet,
@ -30,7 +29,6 @@ class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
val dcacheParams = coreParams.alterPartial({
case CacheName => CacheName("L1D")
case TLId => "L1toL2"
case TileId => tileId // TODO using this messes with Heirarchical P&R: change to io.hartid?
})
val icacheParams = coreParams.alterPartial({
case CacheName => CacheName("L1I")