riscv/rocket-chip
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[rocket] dcache release addr bugfix

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This commit is contained in:
Henry Cook 2016-11-16 12:53:20 -08:00
parent 06a7b95d0d
commit c5e03c9c76
1 changed files with 1 additions and 2 deletions
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src/main/scala/rocket/dcache.scala
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@ -457,8 +457,7 @@ class DCache(maxUncachedInFlight: Int = 2)(implicit val p: Parameters) extends L
dataArb.io.in(2).valid := inWriteback && releaseDataBeat < refillCycles dataArb.io.in(2).valid := inWriteback && releaseDataBeat < refillCycles
dataArb.io.in(2).bits.write := false dataArb.io.in(2).bits.write := false
dataArb.io.in(2).bits.addr := Cat(tl_out.c.bits.address(paddrBits-1, untagBits), dataArb.io.in(2).bits.addr := tl_out.c.bits.address | (releaseDataBeat(log2Up(refillCycles)-1,0) << rowOffBits)
releaseDataBeat(log2Up(refillCycles)-1,0)) << rowOffBits
dataArb.io.in(2).bits.way_en := ~UInt(0, nWays) dataArb.io.in(2).bits.way_en := ~UInt(0, nWays)
metaWriteArb.io.in(2).valid := release_state.isOneOf(s_voluntary_write_meta, s_probe_write_meta) metaWriteArb.io.in(2).valid := release_state.isOneOf(s_voluntary_write_meta, s_probe_write_meta)