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tilelink2 Monitor: enforce stricter transaction ordering

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This commit is contained in:
Wesley W. Terpstra 2016-10-12 18:55:57 -07:00
parent d8a1163131
commit c4eadd3ab3
1 changed files with 3 additions and 7 deletions
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10
src/main/scala/uncore/tilelink2/Monitor.scala
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@ -392,24 +392,20 @@ class TLMonitor(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: Source
val (_, a_last, _) = edge.firstlast(bundle.a.bits, bundle.a.fire()) val (_, a_last, _) = edge.firstlast(bundle.a.bits, bundle.a.fire())
val (_, d_last, _) = edge.firstlast(bundle.d.bits, bundle.d.fire()) val (_, d_last, _) = edge.firstlast(bundle.d.bits, bundle.d.fire())
val bypass = bundle.a.bits.source === bundle.d.bits.source
val a_bypass = bypass && bundle.d.valid && d_last
val d_bypass = bypass && bundle.a.valid && a_last
if (edge.manager.minLatency > 0) { if (edge.manager.minLatency > 0) {
assert(!bypass || !bundle.a.valid || !bundle.d.valid, s"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}" + extra) assert(bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}" + extra)
} }
val a_set = Wire(init = UInt(0, width = edge.client.endSourceId)) val a_set = Wire(init = UInt(0, width = edge.client.endSourceId))
when (bundle.a.fire()) { when (bundle.a.fire()) {
when (a_last) { a_set := UIntToOH(bundle.a.bits.source) } when (a_last) { a_set := UIntToOH(bundle.a.bits.source) }
assert(a_bypass || !inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
} }
val d_clr = Wire(init = UInt(0, width = edge.client.endSourceId)) val d_clr = Wire(init = UInt(0, width = edge.client.endSourceId))
when (bundle.d.fire() && bundle.d.bits.opcode =/= TLMessages.ReleaseAck) { when (bundle.d.fire() && bundle.d.bits.opcode =/= TLMessages.ReleaseAck) {
when (d_last) { d_clr := UIntToOH(bundle.d.bits.source) } when (d_last) { d_clr := UIntToOH(bundle.d.bits.source) }
assert(d_bypass || inflight(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) assert((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
} }
inflight := (inflight | a_set) & ~d_clr inflight := (inflight | a_set) & ~d_clr