From 17134125e1630428d8e7ec90ce1d71d8019a5cb6 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Thu, 24 Aug 2017 23:35:01 +0200 Subject: [PATCH 1/2] SystemBus: remove misnamed functions (#972) These functions were actually for cross connecting chips. --- src/main/scala/coreplex/SystemBus.scala | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala index 501bad37..0eddd8ea 100644 --- a/src/main/scala/coreplex/SystemBus.scala +++ b/src/main/scala/coreplex/SystemBus.scala @@ -29,10 +29,8 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr private val tile_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable)) private val port_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all)) - private val master_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all)) master_splitter.node :=* tile_fixer.node master_splitter.node :=* port_fixer.node - inwardNode :=* master_fixer.node def toSplitSlaves: TLOutwardNode = outwardSplitNode @@ -42,17 +40,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr val toSlave: TLOutwardNode = outwardBufNode - def fromAsyncMasters(depth: Int = 8, sync: Int = 3): TLAsyncInwardNode = { - val sink = LazyModule(new TLAsyncCrossingSink(depth, sync)) - master_fixer.node :=* sink.node - sink.node - } - - def fromSyncMasters(params: BufferParams = BufferParams.default): TLInwardNode = { - val buffer = LazyModule(new TLBuffer(params)) - master_fixer.node :=* buffer.node - buffer.node - } + def fromCoherentChip: TLInwardNode = inwardNode def fromSyncTiles(params: BufferParams): TLInwardNode = { val buf = LazyModule(new TLBuffer(params)) From 103b6bc6d351e290d180bacd5c60e5914d4230a3 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Thu, 24 Aug 2017 14:42:30 -0700 Subject: [PATCH 2/2] systemBus: allowing naming the TLBuffers which get inserted --- src/main/scala/coreplex/SystemBus.scala | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala index 0eddd8ea..30cd999c 100644 --- a/src/main/scala/coreplex/SystemBus.scala +++ b/src/main/scala/coreplex/SystemBus.scala @@ -60,13 +60,16 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr sink.node } - def fromSyncPorts(params: BufferParams = BufferParams.default): TLInwardNode = { + def fromSyncPorts(params: BufferParams = BufferParams.default, name: Option[String] = None): TLInwardNode = { val buffer = LazyModule(new TLBuffer(params)) + name.foreach{ n => buffer.suggestName(s"${n}_TLBuffer") } port_fixer.node :=* buffer.node buffer.node } - def fromSyncFIFOMaster(params: BufferParams = BufferParams.default): TLInwardNode = fromSyncPorts(params) + def fromSyncFIFOMaster(params: BufferParams = BufferParams.default, name: Option[String] = None): TLInwardNode = { + fromSyncPorts(params, name) + } def fromAsyncPorts(depth: Int = 8, sync: Int = 3): TLAsyncInwardNode = { val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))