diff --git a/src/main/scala/coreplex/Configs.scala b/src/main/scala/coreplex/Configs.scala
index 3ed5f2bd..710d1f57 100644
--- a/src/main/scala/coreplex/Configs.scala
+++ b/src/main/scala/coreplex/Configs.scala
@@ -39,6 +39,7 @@ class BaseCoreplexConfig extends Config ((site, here, up) => {
   // TileLink connection global parameters
   case TLMonitorBuilder => (args: TLMonitorArgs) => Some(LazyModule(new TLMonitor(args)))
   case TLCombinationalCheck => false
+  case TLBusDelayProbability => 0.0
 })
 
 /* Composable partial function Configs to set individual parameters */
diff --git a/src/main/scala/tilelink/Bus.scala b/src/main/scala/tilelink/Bus.scala
index 134a14f7..d3c143ae 100644
--- a/src/main/scala/tilelink/Bus.scala
+++ b/src/main/scala/tilelink/Bus.scala
@@ -3,9 +3,10 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.tilelink._
+
+case object TLBusDelayProbability extends Field[Double]
 
 /** Specifies widths of various attachement points in the SoC */
 trait TLBusParams {
@@ -26,7 +27,9 @@ abstract class TLBusWrapper(params: TLBusParams)(implicit p: Parameters) extends
   val masterBuffering = params.masterBuffering
   val slaveBuffering = params.slaveBuffering
   require(blockBytes % beatBytes == 0)
+  private val delayProb = p(TLBusDelayProbability)
 
+  private val delayer = if (delayProb > 0.0) Some(LazyModule(new TLDelayer(delayProb))) else None
   private val xbar = LazyModule(new TLXbar)
   private val master_buffer = LazyModule(new TLBuffer(masterBuffering))
   private val slave_buffer = LazyModule(new TLBuffer(slaveBuffering))
@@ -34,11 +37,14 @@ abstract class TLBusWrapper(params: TLBusParams)(implicit p: Parameters) extends
   private val slave_ww = LazyModule(new TLWidthWidget(beatBytes))
 
   xbar.node :=* master_buffer.node
-  slave_buffer.node :*= xbar.node
+  slave_buffer.node :*= delayer.map { d =>
+    d.node :*= xbar.node
+    d.node
+  } .getOrElse { xbar.node }
   slave_frag.node :*= slave_buffer.node
   slave_ww.node :*= slave_buffer.node
 
-  protected def outwardNode: TLOutwardNode = xbar.node
+  protected def outwardNode: TLOutwardNode = delayer.map(_.node).getOrElse(xbar.node)
   protected def outwardBufNode: TLOutwardNode = slave_buffer.node
   protected def outwardFragNode: TLOutwardNode = slave_frag.node
   protected def outwardWWNode: TLOutwardNode = slave_ww.node