riscv/rocket-chip
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moved PCR writeback to end of MEM stage, cleanup of dcache/dpath/ctrl

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Rimas Avizienis
2011-11-17 23:50:45 -08:00
parent 5a322ff00c
commit c42d8149b7
5 changed files with 58 additions and 104 deletions
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3
rocket/src/main/scala/dpath_util.scala
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@ -51,7 +51,6 @@ class ioDpathPCR extends Bundle()
val cause = UFix(5, 'input);
val badvaddr_wen = Bool('input);
val pc = UFix(VADDR_BITS, 'input);
val badvaddr = UFix(VADDR_BITS, 'input);
val eret = Bool('input);
val ei = Bool('input);
val di = Bool('input);
@ -114,7 +113,7 @@ class rocketDpathPCR extends Component
}
when (io.badvaddr_wen) {
reg_badvaddr <== io.badvaddr;
reg_badvaddr <== io.w.data.toUFix;
}
when (io.exception && !reg_status_et) {