riscv/rocket-chip
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moved PCR writeback to end of MEM stage, cleanup of dcache/dpath/ctrl

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Rimas Avizienis
2011-11-17 23:50:45 -08:00
parent 5a322ff00c
commit c42d8149b7
5 changed files with 58 additions and 104 deletions
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rocket/src/main/scala/cpu.scala
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@ -10,7 +10,6 @@ class ioDebug(view: List[String] = null) extends Bundle(view)
val id_valid = Bool('output);
val ex_valid = Bool('output);
val mem_valid = Bool('output);
val wb_valid = Bool('output);
}
class ioHost(view: List[String] = null) extends Bundle(view)
@ -73,7 +72,6 @@ class rocketProc extends Component
// ctrl.io.itlb_miss := itlb.io.cpu.resp_miss;
io.imem.itlb_miss := itlb.io.cpu.resp_miss;
// connect DTLB to D$ arbiter, ctrl+dpath
dtlb.io.cpu.invalidate := dpath.io.ptbr_wen;
dtlb.io.cpu.status := dpath.io.ctrl.status;